Stream data TO FPGA

[Eldrich]

Hi,

I've seen plenty of examples of how to stream data from the FPGA to a RT host VI.

I'm interested in doing the exact oposite. I have data, (SGL array) in a RT Host VI that i need to process on the FPGA.

Any pointers on how i can do this?

I've tried shared variables and a DMA FIFO with no luck.

-Eldrich

[T-REX$ · Accepted solution]

If you're using LabVIEW 2013, there should be a simple example in the NI Example Finder. It's under CompactRIO->Data Transfer and Storage->Host to Target DMA -> Streaming Data (DMA).lvproj. If you're not running 2013, here's a screenshot of the (very simple) block diagrams.

Host:

Target:

[nathand]

Can you be more specific than "no luck"? A DMA FIFO should transfer data from an RT host to the FPGA, although on some targets the performance is optimized for transfer from the FPGA and is not as fast in the other direction. I recently worked on a project in which a cRIO drove an inkjet printhead. The RT code received an image over the network and streamed it to the FPGA over a DMA FIFO. It worked exactly as intended and met our needs.

[Eldrich]

The exact problem i'm having is this.

I have external VI's that read a stwork stream to produce an array of data. This happens every 20msec.

I'm having trouble writing the data from the RT host to the FPGA VI mainly because (i think) FPGA FIFO's only allow writing of one element at a time.

I haven't looked at the example (answer above) but i will.

Cheers & many thanks!

[T-REX$]

As you can see in the image above, you can actually write in an entire array from the host side. You can only pull out one element at a time on the FPGA side. This is typically fine, since the FPGA algorithm is likely running much faster than the RT code.

[Eldrich]

I will try that and see.

It's exactly what i was looking for.

Is there a way to include the original delay (20msec) when i reconstruct the data (waveform) on the FPGA?

-Cheers!

[nathand]

---

Eldrich wrote:

I'm having trouble writing the data from the RT host to the FPGA VI mainly because (i think) FPGA FIFO's only allow writing of one element at a time.

---

On the RT side, the DMA FIFO functions (both read and write) work with arrays. On the FPGA side, you can read or write only one element at a time. Arrays are generally inefficient on an FPGA. If you need to work with a large array, create a loop on the FPGA that streams it from the DMA channel into an FPGA memory block. FPGA memory is also much more limited than on the RT side, so depending on the size of your array you may need to load and process it in chunks.

[ToeCutter]

Eldrich, forgive me if I'm wrong, but it sounds like you haven't studied the LabVIEW FPGA course (which may well be available freely to you if you have a current LV license).

It may look easy to jump in with LabVIEW FPGA, but it's easy to write very poorly performing code if you don't understand the unique optimisation aspects first.

[Eldrich]

I have!

It's just that the couse covers so many topics that it's easy to forget or ignore sections.

That is, until you use them.

But thanks for pointing that out!

[Eldrich]

I'm compiling the FPGA code now and i hope it works. T-REX$, your pointer to the example worked like a charm, thanks! (i wish there was an option to buy the other person a beer or something like that)

@T-REX$ there's a bit of another problem that i'm going to run into. The logic used in the example code runs the FPGA algorithm as long as the FIFO does't time out.

What i'm trying to do is this:

The RT VI loop rate is 200msec. The FPGA VI loop rate is 50usec. i.e the FPGA VI runs 4000 times for every time the RT VI runs.

The question is this: Should i pause the FPGA VI if the FIFO data runs out? Or is there a more elegant solution (like interpolation, maybe?)

Cheers!

Eldrich