10-25-2007 04:40 PM
10-25-2007 11:28 PM - edited 10-25-2007 11:28 PM
It's not real clear on what you are trying to do, or more so why you are trying to do this. It sounds like you already know how to use the property node of the serial port to assert the DTR line. Correct? It almost sounds like you want to use hardware flow control. But hardware flow control just uses the DTR line (and the others) to control flow depending on the status of the buffer whether it is too full to receive more data, etc. It really has nothing to do with, "hey data is currently coming down the line at this very instant." If you are trying to control the DTR line to do this, I think you have few problems.
One, determining how long to assert the line based on the number of characters and baud rate (not too bad, mostly a math problem).
Two, synchronizing of the setting of the DTR with the actual transmission of data. It sounds like very tight timing you want. I think this is difficult because I don't know how predictable the putting of the data in the serial buffer is relative to the time it actually goes out the line. These is very low level functions that would be a part of the serial driver and the UART hardware.
Three, if you are doing all of this control by way of software timing, I don't think you can get any better than 1 msec timing due to the nature of the windows operating system. It will schedule the tasks of putting the data in the buffer and setting the DTR as it sees fit. I don't think you can syncrhonize them in the sub millisecond range. The use of notifiers, rendezvous's and structures like that may help. But I think it is still very tight timing.
I think to have a chance of doing what you are describing, you would probably have to hard code all of these actions in an FPGA program which would not be trivial.
One other possibility might be to use a high speed digital output card where you can output a defined bit stream and simultaneously trigger another output that simulates the DTR signal on another digital output line. I don't think this would be easy to do, but it might be possible. It would mean simulating the entire serial protocol with start bits, stop bits, parity, intercharacter delay and all of that.
Perhaps you can fill in more details of your application and why you need to do what you are asking. Others may have some better ideas of how to accomplish this task.
Message Edited by Ravens Fan on 10-26-2007 12:31 AM
10-26-2007 12:08 AM - edited 10-26-2007 12:08 AM
Mensaje editado por NavasCOL
10-26-2007 09:59 AM