Synchronization and result representation method between FPGA target and Host Pc

[dream4me]

PID control is being performed using an FPGA device.

The sample rate of the FPGA device is 1,000S/s and the requested depth size of the AI ​​FIFO, that is, the waveform size, is 400.

1. For the above conditions, is it right that the while loop of the host is repeated at a cycle of 400msec? That is, is the waveform size dependent on the repetition period of the while loop of the host?
2. If the contents of the frist question are correct, as the waveform size increases, the graph or indicator value expressed in the host will not be continuously displayed. If the value of graph or indicator is continuously displayed on the host, what method can be used?
3. Suppose the host is programmed to save data when certain conditions are met in the while loop. If the save command is given at any point in time, is the save command delivered only when the while loop repetition period of 400msec is reached? If it is confirmed by the current test, 400 output data offsets are confirmed. How should we approach programming to solve this problem?

[Terry_ALE]

Is this meant to be continuous? Or a single shot?

I would limit host involve to keep the FPGA from being starved of data.

I would add enough buffer to the FPGA so that the host doesn't play too much of a role.

[dream4me]

* Is this meant to be continuous? Or a single shot?

   - My problem is not a single shot but continuous.

* I would limit host involve to keep the FPGA from being starved of data.

  - I don't know the meaning. Can you explain with an example if possible?

* I would add enough buffer to the FPGA so that the host doesn't play too much of a role.

  -  If more buffers are added to FIFO for AI in FPGA and then the host reads them all through the FIFO,

     does the iteration of the while loop of the host depend on the number of elements in the FIFO? 

[Bob_Schor]

I'm confused by the Title of this post, describing communication between an FPGA Target and a Host PC.  In my somewhat-limited experience (I've only been doing FPGA stuff for less than two years), the FPGA is part of a LabVIEW Real-Time (what I call a) Target system, and in my case, communicates with a Windows PC running LabVIEW using TCP/IP.  I call the "PC running LabVIEW" the "Host" system, and the Real-Time (often a RIO-type) device running the LabVIEW-RT OS the "RT Target".

Because LabVIEW-RT is not optimized for Front Panel interactions (including Graphs and Charts), I've been streaming data (using Network Streams) straight from the RT Target to the Host PC and doing all my File I/O and "User Interaction with the Data" (including viewing it) on the PC side.  It doesn't sound, to me, that this is what you are describing.  Maybe you can clarify (or, much better, provide all of the relevant LabVIEW code, as .vi files, of course ...).

Bob Schor