Three Counters in PXI-6259

[P. Jack]

Hello Everyone,

I'm trying to measure time t in the picture that I have attached. I am using a PXI-6259 for this (both input and output). My first idea is to use one counter to generate the input, another counter to time when to stop the first counter and the third counter to measure time t. However, I find difficulty in getting the timing correctly, especially, the second timer.

Do you have any ideas on how to do this?

Thanks

[David L.]

Hi P.Jack,

I would like to ask for a bit more information about your project and DUT. Creating a pulse as input for the DUT is not a problem. Examples can be found in the LabVIEW example finder ((Help >> Find Examples… >> Hardware Input and Output >> DAQmx >> Generating Digital Pulses). Please keep in mind that the finite pulse train uses both counters (one to generate the train, and one to count the number of pulses that have been generated). Continuous generation only uses one counter, leaving you with a free one. On that note, I would like add that the 6259 only has two counters.  

Is the DUT output a TTL signal ? Also, is this a stimulus response system, where t can vary in the time it takes? (that is the impression I gathered from the picture). The overall task you are looking to accomplish cannot be completely done in hardware with the PXI-6259 because there are only two counters on the board, and this entire program would require four counters.. If hardware timing is essential, I would suggest a PXI-6602 counter/timer card. This will allow you to use two counters to create the pulse train, and another two to do a buffered counter acquisition.

If partial software timing is OK for this project, than the 6259 can accomplish the task. I would do a pulse generation, and then once this is complete (time T starts), you can clear the task and create a buffered counter task. Instead of creating another task, you may also think about doing a digital read on the input line. You would put the read in a loop, and constantly monitor the line until it goes low. You would put tick counts before and after the loop, then compare them and see how long it took for the digital line to go low. Either route is software timed because it requires configuring and starting a new task at a minimum.

[P. Jack]

Can I just do it this way:

1. Create a task (Task1) of "Continuous Pulses" using one counter.

2. Create a task (Task2) for a digital monitor of the DUT out.

3. All in sequence In LabVIEW, I'll start Task1.

4. Next frame, I'll use a while loop to monitor DUT out using Task2 until TRUE (or HIGH).

5. Next frame, wait for 10ms (Wait (ms))

6. Next frame, stop Task1 and use Tick Count (ms) to record time.

7. Next frame, use Task2 in a while loop to monitor DUT out until FASLE (or LOW)

8. Next frame, use Tick Count (ms) to record time and get time t using the difference of the recorded time.

With this, what do you think will be my main problem? What is the weakness of this code?

Will I get time t as accurately as possible? If not, about how much will it deviate?

[falkpl]

Drop the sequence for a state machine architecture.  The reason for this is flexability.  You can handle out of order steps, more robust error handling and easily reuse and add steps to this architecture.

Paul

[P. Jack]

OK, I get that. But with this illustration, will it be enough tocover my problem.

[TheWoost]

Hi,

The pseudocode that you have will certainly get you the t value that you are looking for (whether it be done in a sequence or in a state machine).  However, it's hard to say how precise of a measurement this will be because you are depending solely on software timing to calculate the value.  If you are looking for more precise hardware timing I would recommend David's earlier suggestion of using a counter/timer board.

Regards,
Andrew W
National Instruments

Message Edited by TheWoost on 05-02-2007 12:45 PM

[P. Jack]

Right now, my only hardware is 6259. Well, thanks everyone.

[P. Jack]

Hello again, I am looking into using a NI PXI-7811R module. This is an FPGA and I can say that it is quite different on how we normally do FPGA design (Verilog, VHDL, etc.). But, can I achieve what I wanted with this module?

It says it has 1M gates for 160 I/O. For an Altera or Xilinx FPGA, you can do anything you wanted as long as clock is OK. I can build too many counters and can still use much more I/O for other data acquistion. But it can only operate at 40MHz, at most, though. What do you think, what am I missing?

[Xaq]

P. Jack-

You shouldn't have any problem implementing your applications with a 7811R. You will need to use the LabVIEW FPGA module to program for it (versus a more traditional language like Verilog or VHDL). The default clock on the 7811R is 40Mhz, but you can create derived clocks up to 200Mhz (assuming your code can execute that quickly).

As you mentioned, you can use up to 1M gates to implement your design. So if your implementation for the above design only uses a fraction of the gates available, you can use the rest for another design (both must be in the same FPGA VI).

Xaq