Timing constraint: COMP "d<23>" OFFSET = OUT 15.3 ns AFTER COMP "MiteClk";

[Idratherberacing]

I am using DMA FIFO's to move data from the target to the Host for processing.  Apparently, this is causing an issue that I've never had to deal with before.  Does anyone have any insight here??  Can I adjust this offset that is called out below??

This is the report from the compiler...

Status: Compilation failed.

Refer to the advanced tab for more information, or contact National Instruments technical support at ni.com/support.

Compilation Summary
-------------------

Device Utilization Summary:
   Number of BUFGMUXs                        2 out of 16     12%
   Number of External IOBs                 263 out of 484    54%
      Number of LOCed IOBs                 263 out of 263   100%
   Number of RAMB16s                         6 out of 96      6%
   Number of SLICEs                       8280 out of 14336  57%

Clock Rates: (Requested rates are adjusted for jitter and accuracy)
  Base clock: 40 MHz Onboard Clock
      Requested Rate:      40.408938MHz
      Theoretical Maximum: 40.945011MHz

================================================================================
Timing constraint: COMP "d<23>" OFFSET = OUT 15.3 ns AFTER COMP "MiteClk";

 14 items analyzed, 1 timing error detected.
 Minimum allowable offset is  15.883ns.
--------------------------------------------------------------------------------

================================================================================
Timing constraint: COMP "d<22>" OFFSET = OUT 15.3 ns AFTER COMP "MiteClk";

 14 items analyzed, 1 timing error detected.
 Minimum allowable offset is  16.238ns.
--------------------------------------------------------------------------------

================================================================================
Timing constraint: COMP "d<21>" OFFSET = OUT 15.3 ns AFTER COMP "MiteClk";

 14 items analyzed, 1 timing error detected.
 Minimum allowable offset is  15.745ns.
--------------------------------------------------------------------------------

================================================================================
Timing constraint: COMP "d<20>" OFFSET = OUT 15.3 ns AFTER COMP "MiteClk";

 14 items analyzed, 1 timing error detected.
 Minimum allowable offset is  15.404ns.
--------------------------------------------------------------------------------

================================================================================
Timing constraint: COMP "d<19>" OFFSET = OUT 15.3 ns AFTER COMP "MiteClk";

 14 items analyzed, 1 timing error detected.
 Minimum allowable offset is  15.800ns.
--------------------------------------------------------------------------------

================================================================================
Timing constraint: COMP "d<18>" OFFSET = OUT 15.3 ns AFTER COMP "MiteClk";

 14 items analyzed, 1 timing error detected.
 Minimum allowable offset is  15.538ns.
--------------------------------------------------------------------------------

================================================================================
Timing constraint: COMP "d<17>" OFFSET = OUT 15.3 ns AFTER COMP "MiteClk";

 14 items analyzed, 1 timing error detected.
 Minimum allowable offset is  15.944ns.
--------------------------------------------------------------------------------

================================================================================
Timing constraint: COMP "d<16>" OFFSET = OUT 15.3 ns AFTER COMP "MiteClk";

 14 items analyzed, 1 timing error detected.
 Minimum allowable offset is  15.693ns.
--------------------------------------------------------------------------------

================================================================================
Timing constraint: COMP "d<7>" OFFSET = OUT 15.3 ns AFTER COMP "MiteClk";

 14 items analyzed, 1 timing error detected.
 Minimum allowable offset is  15.715ns.
--------------------------------------------------------------------------------

================================================================================
Timing constraint: COMP "d<6>" OFFSET = OUT 15.3 ns AFTER COMP "MiteClk";

 14 items analyzed, 1 timing error detected.
 Minimum allowable offset is  15.612ns.
--------------------------------------------------------------------------------

================================================================================
Timing constraint: COMP "d<1>" OFFSET = OUT 15.3 ns AFTER COMP "MiteClk";

 14 items analyzed, 1 timing error detected.
 Minimum allowable offset is  15.496ns.
--------------------------------------------------------------------------------

================================================================================
Timing constraint: COMP "d<0>" OFFSET = OUT 15.3 ns AFTER COMP "MiteClk";

 14 items analyzed, 1 timing error detected.
 Minimum allowable offset is  15.422ns.
--------------------------------------------------------------------------------

[Idratherberacing]

I disabled one of the DMA FIFOs and now it compiles.... Why would using 3 DMA FIFO's instead of 2 make a difference??

Status: Compilation successful.

Compilation Summary
-------------------

Device Utilization Summary:
   Number of BUFGMUXs                        2 out of 16     12%
   Number of External IOBs                 263 out of 484    54%
      Number of LOCed IOBs                 263 out of 263   100%
   Number of RAMB16s                         4 out of 96      4%
   Number of SLICEs                       8022 out of 14336  55%

Clock Rates: (Requested rates are adjusted for jitter and accuracy)
  Base clock: 40 MHz Onboard Clock
      Requested Rate:      40.408938MHz
      Theoretical Maximum: 40.908161MHz

Start Time: 9/15/2009 12:31:53 PM
End Time: 9/15/2009 1:13:37 PM

[Ruhmann]

OK, these are timing errors within the FPGA.  Well, not actually on the FPGA, but the Xilinx tools concluded that there would be timing errors while transferring data to and from the FPGA.  To simplify the reason, when you add another DMA FIFO, LabVIEW has to place more logic between the PCI bus and your VI in order to arbitrate the one PCI bus between the many FIFOs.  Still, it's very frustrating to see these errors.  Are you using LabVIEW 2009?  If so, you can try increasing the Xilinx compile effort.  Also, you can try removing anything that may not be necessary from the FPGA VI.  This will leave more room on the FPGA for the Xilinx tools to work with when trying to find the most efficient routing.

To be honest, I'm really shocked that you saw this error on a Virtex 2 based device.

[Idratherberacing]

I'm using LabVIEW 8.5

[Idratherberacing]

Here is the LabVIEW FPGA VI for reference.  I have attached the PWM Generator subVI and to get it to run with one of the FIFO's disabled, you'll have to add 3 DMA FIFO's to a project that are a depth of 64, and of U32 type...

[Ipshita_C]

Hi,

I have attached this knowledgebase article for your reference. You should not have trouble using 3 DMA FIFOs unless you are running your project in hybrid-mode or your RIO driver version is an old one. I would also have a look at this knowledgebase article. Amount of memory to be used on DMA FIFOs used to hardcoded in older RIO versions. Hope this helps!

Ipshita C.

[Idratherberacing]

I'm using NI RIO 3.1, so that's not the issue.  The board is a PXI-7813R and I'm not sure if it's in hybrid mode... Where would I find that??

[Ruhmann]

Idratherberacing,

What it really comes down to is that you have way too much logic within a single cycle timed loop.   I understand that some of your digital logic may require a SCTL, depending on the requirements of your application, but you shouldn't put everything in a SCTL.  I can't really understand everything you have in your VI, so I'm not sure what actually needs to be done in a single cycle and what doesn't.  I'm sure you can find a way to seperate this code into many parallel loops without so much logic inside one SCTL.  The FPGA needs to find a way to place the needed gates together to get signals from the left of your diagram all the way to the right of your diagram, through all those selects, cases, and compares, in well under 25ns.  The propogation delays on all those gates just won't allow it.  If this diagram is outside of a SCTL then the FPGA can put registers between all the nodes and timing becomes far less of an issue.   This problem may also be solved by rearranging your code to allow for shorter, parallel data paths through the loop.

[Idratherberacing]

I thought about doing parallel loops and when I implemented it, the timing between the two was offset, so they weren't truly parallel.  If there's a way I can sync them up, that'd be perfect.

[Ruhmann]

In this case parallel data paths in the same loop is no different here than multiple parallel loops.  You need to do fewer things in each iteration.  For instance, you can follow the wires and figure out the path that is the longest (goes through the most nodes) and try to shorten that somehow.  Maybe you can use shift registers in a way where you are pipelining your process.  That is, doing half the operation in one iteration then sticking your current data in a shift register and pulling it out on the next iteration to finish the operation.

Do you need to use the single cycle timed loop for everything?