Timing error in my fpga code

[kprabaka]

Hi T-REX$, 

       One final question. How will this feedback affect the RMS measurement.

-Kumar

[T-REX$]

Just having the feedback node won't really affect the measurement at all. It will introduce a single clock-cycle of latency, meaning that Data Valid will turn true 1 cycle later the first time. Having the FXP conversion VI could have a much larger effect on the precision and/or range of your data depending on how it's configured. I would try with just the feedback node first to see if that gets you compiling. If that alone isn't enough, I'd start looking at optimizing the FXP portion of your code.