LabVIEW

cancel
Showing results for 
Search instead for 
Did you mean: 

Trigger Slave Chassis default state on RT program abort

I have a project with user-defined variables as well as IO variables directly to the card.

In the realtime application when i hit "abort" my program crashes. but the IO (analog out and Digital out) for my slave NI 9145 remain the same.

elibarber_0-1764785515401.png

I need the slave to revert back 0 for analog out and false for digital out, in the even that my program crashes. How can I implement such a feature? Do I need to use the  or can i use something else? Is there a recommended way of doing so?

 

0 Kudos
Message 1 of 5
(120 Views)

In the past 2 or 3 months, I've noticed numerous posts asking how to make the "abort" button work properly.  The most common answer (by users who are even more experienced and knowledgeable than I) is "NEVER USE THE ABORT BUTTON" (some even go so far as suggesting you hide this Control).

 

When you detect a situation when an "Abort" seems to be necessary, you don't want to stop the computer from running, but want to perform an "orderly" (and programmed) series of steps.  In your case, you need to tell the Real-Time side to go to a "Shut-down" routine that sets the hardware as you want it (A/D, D/A, and Digital I/O, plus perhaps others) and stop all the parallel loops in an orderly manner.  On the Host, you need to do the same things, and also close any open files.

 

Bob Schor

0 Kudos
Message 2 of 5
(111 Views)

Bob,

 

I am trying to simulate a crash, not safely abort the program. This is exactly why I need this logic to work with abort.

 

 

0 Kudos
Message 3 of 5
(94 Views)

See shipping example Hardware Input and Output >> NI-Industrial Communications >> EtherCAT >> Advanced >> Safe Value with FPGA.lvproj

 

Make sure Watchdog is enabled.

  • Right-click on the NI-9145 and select Properties.
  • Under Advanced:Watchdog, enable sync manager watchdog and set a timeout.

 

When the EtherCAT crashes and stops sending datagram, the watchdog timeouts and the slave transitions to Safe-Op state.

-------------------------------------------------------
Applications Engineer | TME Systems
https://tmesystems.net/
-------------------------------------------------------
https://github.com/ZhiYang-Ong
0 Kudos
Message 4 of 5
(71 Views)

ZYOng,

 

That will work for user defined variables. But I also have Real-Time Scan IO Variables. Not controlled by the FPGA. So I only have read access apparently. What can I do? They are not present as IO nodes to manipulate either.

elibarber_0-1764864776975.png

 

elibarber_1-1764864857449.png

elibarber_2-1764864944947.png

elibarber_3-1764864990739.png

 

 

 

 

0 Kudos
Message 5 of 5
(48 Views)