Tristate buffers + shared bus in LabVIEW

[ijustlovemath]

I know I could use a for loop to iterate over a cluster, and store just one result in some register based on the value of gate signals. But are there any "analog" ways to simulate this structure in LabVIEW?

[johnsold]

I am not sure what you are trying to do. A floating point numeric value could probably be used to represent your "analog" signal. A shift register and a case structure seems like a possible approach.  One case could place a new value on the shift register. Another case coud pass the previous value through. The tristate or high impedance state could be modeled in a third case, although I don't know what value you would choose.

Lynn

[ijustlovemath]

Simulating a microcomputer. There's a bunch of 16 bit signals that have access to a shared bus via tri state buffers. A micro controller issues activation signals to the gates, passing the signals onto the bus, where they are then taken in via other buffers. Here's a picture: http://users.ece.utexas.edu/~patt/11s.460N/probs/ps5/ps5.html

That thick black line is the bus in question. Ideally, I could make my block diagram look like that, save for a few subVIs. Is that possible?

[ijustlovemath]

https://www.google.com/search?q=lc3+block+diagram&client=safari&hl=en&prmd=isvn&source=lnms&tbm=isch...

Better picture with less text

[johnsold]

OK.  I see what you are trying to do.  Interesting project.

First consider what happens in hardware. One of the six buffers is gated on to place data on the bus. Then any and all devices which want to use that data read the bus. The devices reading have no way to know which buffer is driving the bus or whether none of them are doing so.  They can only assume that the correct gate signals have been issued at the correct times.

Assuming that you are doing a logical simulation and not a circuit level simulation, I would go with the shift register/case structure approach. The buffer gate signals drive the selector of the case structure. The output is the bus. I would have one case for each of the six buffers, one for tristate (generate a random value - make it likely something will misbehave if it is used), and one or more for the case(s) where two or more gate signals are True simultaneously (XOR the inputs?). That does not force the assumption that the simulation of the generation of the buffer gate signals is without errors.

The Block diagram will look somewhat different at least as far as the bus drivers are concerned because they will not be distributed around the diagram.

Please keep us posted.

Lynn

[ijustlovemath]

That's how I've designed it thus far. I was just wondering if there was a way to make the block diagram look more recognizable. Thanks for the input!