Trying to make a testbench to check output values from I/O node

[erlingborn]

Hello there! I am trying to make a testbench for a I/O node with analog and digital signals. I want to look at the output and see what i get. I have already made the code for the FPGA and the testbench code but it seems like i don't get them to work together... I have followed the steps from National Instruments: http://www.ni.com/white-paper/8668/en/ The only difference is that i have changed the case structures in the TestBench so it matches my I/O nodes.

Hope i can get some help 🙂

[ShazilM]

Hi erlingborn, 

When you say you cannot ge tthe testbench code to work together with the FPGA code, what exactly do you see?

Do you see any error message? Behaviour that is not expected? 

Your FPGA VI seems to have a true constant tied to the stop button of the while loop, which means that it will not run?

Best Regards,

[erlingborn2]

It does not matter if I tie a False constant to the stop button. The problem is that the testbench wont go into the "running" case mode, it stops in the "initializing" case. 

Best regards,

Jesper