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Tunnel conditional not allowed with fpga target. Any alternative?

Hi, I am working to a project with a cRIO device and I have done a code for selecting values from a function, called Get Time, included in the FPGA timekeeper library. I tried to use conditional tunnel but the arrow is broken. Is there any alternative to tunnel conditional for selecting values?
I attached the file.
Thanks

Message 1 of 17
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Use a shift register and a selector:

 

Alternative for conditional last value.png

 

(I used a constant Boolean and numeric, hoping you get the drift).

 

As a bonus, you get to choose the default value, the value that's returned when the loop stops without ever getting a true on the condition. 

Message 2 of 17
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@Loop3r_III wrote:

Hi, I am working to a project with a cRIO device and I have done a code for selecting values from a function, ... Is there any alternative to tunnel conditional for selecting values?
s


Obviously I don't quite "get" your question and your VI. Can you explain in a few more words what "selecting values from a function" actually means? What value do you expect if the loop stops and the boolean is false? Why should the loop stop and what happens afterwards? Is this part of some bigger code?

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Message 3 of 17
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The function Get Time gives in output a time that increases during the while loop. My idea was to send Get Time output out of the while loop using conditional tunnel, but I cannot do this with the target fpga I am using. So I am looking for a code that make the same thing of conditional tunnel. I hope I am more clear:)

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@Loop3r_III wrote:

I am looking for a code that make the same thing of conditional tunnel. I hope I am more clear:)


Am I crazy or are you just talking about wanting to conditionally build an array just like we all used to have to do before the conditional terminal *tunnel was introduced?

 

conditional array build.png

 

_______________________________________________________________
"Computers are useless. They can only give you answers." - Pablo Picasso
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Message 5 of 17
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Hi to both of you, Loop3r and rwunderl,

 

in LabVIEW FPGA it is NOT ALLOWED to create arrays of variable size!

Arrays need to be fixed in size! (And addtionally only 1D arrays are supported…)

 

This will prevent using conditional tunnels to build arrays and it will also prevent using the "classic" shiftregister+BuildArray approach to build an array…

 

I am working to a project with a cRIO device and I have done a code for selecting values from a function, called Get Time, included in the FPGA timekeeper library. I tried to use conditional tunnel but the arrow is broken.

The questions with your example VI are:

  • Why do you need a conditional tunnel at that very place in your code?
  • Why do you need a stop button in the FPGA VIs?

Please explain WHAT you want to achieve and don't focus on HOW you want to achieve something!

 

The function Get Time gives in output a time that increases during the while loop. My idea was to send Get Time output out of the while loop using conditional tunnel, but I cannot do this with the target fpga I am using. So I am looking for a code that make the same thing of conditional tunnel. I hope I am more clear:)

Not at all!

  • Why do you want to "send a value out of the loop" using a tunnel?
  • Why do you think you need a conditional tunnel?

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
Message 6 of 17
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How about using a shift register and a selector?

 

Alternative for conditional last value.png

 

I agree that the situation is a bit weird, but this is the way to get the same result as a conditional tunnel with last value, as posted as the problem.

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Message 7 of 17
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@GerdW wrote:

in LabVIEW FPGA it is NOT ALLOWED to create arrays of variable size!

Arrays need to be fixed in size! (And addtionally only 1D arrays are supported…)



Forgot about that little detail. It's been a little while since I needed to use FPGA code, and I've slept since then. I knew it couldn't be that simple...

_______________________________________________________________
"Computers are useless. They can only give you answers." - Pablo Picasso
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Message 8 of 17
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@rwunderl wrote:

@GerdW wrote:

in LabVIEW FPGA it is NOT ALLOWED to create arrays of variable size!

Arrays need to be fixed in size! (And addtionally only 1D arrays are supported…)



Forgot about that little detail. It's been a little while since I needed to use FPGA code, and I've slept since then. I knew it couldn't be that simple...


If you have a known maximum that isn't very large you can initialize an array at that size and have a counter that inserts the item into the but only counts up when it gets a true. When the loop ends you have the counter to tell you how many of the items in the array are "valid". For large data sets I've used a similar approach but with the DRAM FIFO API.

Matt J | National Instruments | CLA
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Message 9 of 17
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@rwunderl wrote:

@GerdW wrote:

in LabVIEW FPGA it is NOT ALLOWED to create arrays of variable size!

Arrays need to be fixed in size! (And addtionally only 1D arrays are supported…)



Forgot about that little detail. It's been a little while since I needed to use FPGA code, and I've slept since then. I knew it couldn't be that simple...


But there are no arrays in your original code! Your conditional tunnel is not autoindexing.

 

As others have said, your code makes very little sense, conditional tunnel or not. 

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Message 10 of 17
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