Two independent counter output 6071-E

[cszym001]

I have an application that requires two counter outputs.  The first output must be a continuous PWM (counter 0) and the second counter pulse (counter 1) should be a single pulse triggered every five pulses or so of the continuous pulse train (Counter 0).  However, I need the second pulse to delay an amount each time it is retriggered.  For example After the fifth pulse of counter 0, counter 1 pulses at delay 0.00.  After the 10th pulse of counter 0, counter 1 pulses at a delay of 0.10 from counter 0........15 pulses delays 0.20 and so on until the delay  reaches 1.00 then the program stops.  How would I acheive this is there any examples for a similar code?

Thanks

Chris 

[Hillman]

Hi Chris,

The aspect of counting say 5 clock pulses from counter 0 and then outputing a pulse is possible. The aspect of adding an abritry delay in I dont think is. Is the delay aspect important?

If it was, then I feel FPGA would be the only way to go, as the concept of counters doesnt really exist - you can just do what you like.

If your not worried about the delay then, either,

Using two counters on the same time base being triggered by the same digital trigger could be used, then divide it down. Or have two counter tasks running on carefully chosen frequencies. (i.e 10 and 2).

Let me know what you think,

I also read this KB
http://digital.ni.com/public.nsf/websearch/26CCE4F74DACFD1886256DCF006B011A?OpenDocument Document ID: 32TCEC6I

and Take a look at the following shipping examples in LabVIEW:

Gen Dig Pulse-Retriggerable.vi

Gen Dig Pulse Train-Continuous-Dig Start.vi   ---- may give you some ideas.

[Hillman]

Hi Chris,

Me and another AE, have worked for a little bit on the option I mentioned, on having two counter tasks, using the same trigger and altering the number of ticks to generate the second pulse at 5 ticks of counter 0 with a slight delay everytime.

I have attached the vi's. Counter test produces the two pulse trains, and the cont acq&graph is from the find examples to allow us to view the pulse trains.

We are using two counters from a signal accessory into our cDAQ using an 9215 AI simultaneous card.
Both counters are using the same time base - 20Mhz.
Counter 0 outputs 1 pulse for every 5000 high and 5000 low. i.e. Outputs at a frequency of 2KHz.
Counter 1 outputs 1 pulse for every 25010 high and 25010 low. i.e. five times slower + a bit of a delay.
Everytime we count 5 - the delay adds up, eventually you can see the two counter outputs return to being inphase. 
The only way we can think of ending once the counters have returned to being inphase is to time the task out.. knowing that it takes 'x' amount of time until they're back in phase.

I hope this helps you out,
but if you wana talk more, I'd be interested to know what time base your planning to use and I notice that the 6071E only supports analogue triggering..


Message Edited by Hillman on 08-05-2008 03:37 PM