11-19-2014 10:29 AM - edited 11-19-2014 10:34 AM
Hi,
We are looking to purchase a USB-7856R to start prototyping with FPGA technology for future projects. I have been playing around with the FPGA examples in LabVIEW. I set up a simulated FPGA Target for the USB-7856R. When the target is set up in my project it lists a 40 MHz Clock in the target.
Why is this? The USB-7856R is spec'd with an 80 MHz Clock.
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11-19-2014 11:06 AM
The FPGA has a base clock of 40MHz. The DIO can be clocked at 80MHz. You can make an 80MHz derived clock from the 40MHz clock.
11-19-2014 04:51 PM
You asked a similar question earlier and got a similar answer.
11-21-2014 08:40 AM
Actually Bill,
It was two different questions.
One was regarding how the examples where setting the timed loops to 4 times the base clock in the hardware. The answer was derived clocks, which at the time, was unfamiliar to me.
The second was, why, if the USB-7856R has an 80 MHz clock, as stated in the specification, does it show a 40 Mhz base clock when you look at the configuration information for that target?
When you look at the configuration information for a PCI-7831R, for instance, the base clock is a 40 MHz clock. It just so happens that the card is equipped with a 40 MHz clock so the 40 MHz clock is the base clock and any other clocks the programmer creates are derived clocks.
The USB-7856R, on the other hand, should show an 80 Mhz base clock, because that is what the module is equipped with. So saying that the 80 MHz clock is derived is technically inaccurate. The configuration should reflect the actual configuration of that module not a generic number for the base clock.