LabVIEW
Unable to correctly port PC PLL VI to FPGA
Hello, I am trying to design a PI-based PLL, and I was able to create a functioning one on the PC LabVIEW, but I am struggling with getting it to work on the myRIO FPGA. I would greatly appreciate it if someone could assist me with getting this working, as I do not know what it going wrong. On the PC, I can change the phase increment of the ADC sine wave generator, and the NCO phase increment follows like a PLL should. However, when I try this on the FPGA, I can change the frequency (part of the phase) of the ADC NCO, but the NCO that tracks does not update its value.
As an overview, I have an ADC that takes a external sine wave a some frequency and sends it to a different loop where it is mixed with an NCO sine and cosine signal.
"ADC", but I use a separate NCO that I call ADC so that I may simulate the AI signal
After being mixed, the mixed sine and cosine waves are sent to a LPF, then the result is sent to a phase detector to detect the phase difference between the NCO and ADC.
NCO and Mixer. After mixing, the mixed signals are channelized, then sent to a single FIFO
CIC-based Low-pass filter
This is an LIA algorithm. This detected phase difference is the PLL phase error signal, and it is sent to a PI control to be scaled for usage at the NCO's phase accumulator. Throughout this process, the NCO's sine is sent to the DAC so that I may read it on an external oscilloscope.
Phase detector and PI control
Now, this works on a PC vi that I made, but it does not work on an FPGA version where I used the same logic. I have no idea why it does not work, and I was hoping that someone may assist me. Could my FIFOs be incorrectly utilized? Can I not use the Sine Generator? Are there missing scaling factors?
I have attached my project below so that you may view my code. There are a lot of vi's, however, since I made various iterations to try to fix this issue. For the PC vi, view "PC_PLL_2" and/or "PC_PLL_3" under the project path "My computer -> PLL". For the FPGA vi, view "CustomPll_Pll_4-NoOutRawSine" under "FPGA Target -> PLL -> withoutOutput".
- Best regards, 2001J
