Unable to run Timed Loops

[thoult]

Bit of an odd one that had me scratching my head.

I have a development system consisting of a PC running a 7842R, acquiring analogue and digital data from the FPGA, loading it into a shared variable, and reading it out within a timed loop on the host as one parallel loop in a producer-consumer architecture.

All's well until one day last week when I noticed my host VI becoming unresponsive.

After a bit of digging, I find that the timed loop doesn't run at all. Replacing with a while loop with a wait at least allows me to show that the error is timed loop related, but it's not a viable long term option for me. Creating a new project and a new VI with a simple timed loop showed the same behaviour.

A restart of the system, and rerunning the same VIs, and no problems since.

So, questions:

1) Has anyone else seen this behaviour?

2) Any idea what causes it? A service crashing, for example?

3) Is there a way of recovering without a reboot? If it's a service crash, I'm hopeful.

The system will eventually form part of a production test environment, hence the query.

Edit - also, wiring error terminals of a timed loop is a good way of highlighting errors of course.

FWIW, LV2012 SP1 32bit, Win7 64bit, Core2 Duo, 4GB RAM, tassels from the handlebars etc.

[Lennard.C]

Hi thoult,

Can you attach the vi(s) and LabVIEW Project file related to that problem? I would like to look at the cause of the problem.

And when you mention PC running a 7842R, I would presume it is PCIe 7842R?

Thanks

Warmest regards,

Lennard.C

[thoult]

I'm unable to post the VIs or project due to commercial restrictions, but the Optimizing timed loop rate example in Example Finder is another that I'd tried which failed to execute and returned an -816 error if the loop terminals were wired correctly. The timed loops all had unique, autogenerated names as far as I could see.

And yes, it's a PCIe 7842R.

[GerdW]

Hi thoult,

just an idea: sometimes TWL have problems when you use copy&paste to create them. They have to have unique names to run properly - copying them sometimes fails to create a new (unique) name so the compiler throws errors...

[thoult]

Hey GerdW,

Thanks for the suggestion - I raised this previously in BreakPoint as I too have experienced these before, and I found a KnowledgeBase article which hints at something along those lines.

However, the timed loops here had unique names and were generated individually in this case. Following the KB advice to changed to a while loop and then change back to 'regenerate' the Timed Loop (like Doctor Who?) made no difference - no timed loop would run whatsoever on the system.

Ideally I'd like to know whether it's an issue that disappears once a VI is built into an executable, as an unpredictable corruption of timed loops in a piece of production software would be somewhat fatal to my test platform!

[Dave.T]

Is there a reason you're using timed looped over just a while loop with a wait in it? 

Timed loops are most often used in either the FPGA for single cyle timed loops, or on real time targets where you want to set the loop time with a low amount of jitter. 

If you want to use the Timed Loop in a Windows application it might, if not handled in a manner with respect to the amount of available resources in the system, increase the likelihood of unpredictable behavior. This is because of the preemptive nature of the structure which could monopolize system resources. If you have multiple Timed Loops running simultaneously in your application it may, depending on the amount of Timed Loops used in conjunction to the system resources, enter a deadlock where no time is scheduled to some of your loops, because the processor is occupied and it will seem like part of your application is not executing.

I would recommend using the standard while loop with a wait. 

[thoult]

The timed loop is used to read all elements from a DMA FIFO and load them into a buffer FGV, which spits out packets of N samples long once they've assembled within the FGV. Ordinarily, I'd do this with a timed while loop and be perfectly happy to do so. However, the elements are actually an interleaved array, meaning that I have to demux them in the correct order that they were loaded.

I use timed loops for a number of reasons: on my current Windows host, I've found that using a while loop has caused me more problems with respect to disordered packets, and that at least with using multiple timed loops (two, at most), I can assign priority to the acquire loop. Finally, it's also a development platform, and will be deployed onto an sbRIO once the electronics integration is finished in a week or two!

W.r.t. system resources, there's very little else running on that system, but that doesn't normally stop Windows 🙂

I recognise it's not ideal to run a software timed loop under Windows, but when you cannot run a blank project with Optimizing timed loop rate.vi from the shipped examples with nothing else running, it makes me curious to know why!