User Defined Refnum Error

[rex1030]

I am getting an error that doesn't make any sense to me. I am writing a VI that runs on a cRIO device with an eight channel FPGA backplane. I am trying to connect a FPGA Reference out of one VI to the FPGA Reference in of a sub VI. I am getting an error that states "You have connected two wires of different types. The type of the source is user defined refnum. The type of the sink is user defined refnum. "

Can someone tell me what is causing this error? I am posting a screenshot that shows the main VI in the background with the broken wire, the subvi is in the bottom left and the error messages are on the right. I am also going to post the VI, though I am not sure you will be able to open it without the rest of the project (which I cannot post). Let me know if you need the subVI as well, though.

Message Edited by rex1030 on 08-14-2008 12:58 PM

[rex1030]

I fixed it. I had reformatted the cRIO to install 8.6 and I needed to name the FPGA alias in MAX to what it was when we compiled it. That way the reference refers to the name in the compiled bitfile. I think.

[Jared_B]

rex1030,

To help this from happening again, please see the following KB article.  If I understand correctly, this is the same thing that was happening: Why Do I Have a Broken Wire When Passing My FPGA VI Reference Into a SubVI?

[rex1030]

Ok, I though I had fixed it but I didn't. I tried to do what that article said but I dont know how to do step 2 of the solution.

How do I "Open the SubVI and replace the original FPGA VI Reference Out control with the new Type Definition?" I really don't understand how to replace the output control with a new type definition. Someone help

[Jared_B · Accepted solution]

rex1030,

On this part you will want to open up your SubVI and where you have your FPGA Reference on the block diagram, delete it.  The previous step in the KB article has you create the TypeDef (.ctl).  You can just drag this from your project explorer window to the block diagram of your SubVI and replace it.  

The typedef should take the place of the reference that you currently have wired up.

[Lars Kuur]

I cant make this solution work in LW09, i simply cant pull the .ctl file from the Project Explorer into the VI.

So now i got a project with a typedef and everything, but no working connection between the main and sub_vi....

Please help anyone

[David_L]

What do you mean you can't pull the ctl file into the VI?  Do you get an error?

[IanGuest]

Good morning

I am experiencing the same problem and am having the same results. I am using LV2009 and when I modify the bitfile name, the wires to the sub-vis break. I have also made a type definition, but am unable to place it in the subvi.

I have also tried dragging it and get a "not allowed" symbol (red circle with a diagonal line). The only way I have solved this is by redoing the whole subvi from scratch. Please help - this is very frustrating and is slowing the project down that I am working on.

Regards

Ian

[Anna_K.]

Hello,

this is a bug in LabVIEW 2009. The bug number is 179896 for your reference. The workaround is to create a control off the Open FPGA VI Reference and place that in the Typedef created. ( notice the custom control was empty - this is the bug ).

Thanks,

Anna K.

[jejackson]

I opened up the NI document NI 9870 - Continuous Serial Read - On-Demand Write that included the zip file: 9870_serial_read_write_lv9.zip. In the host vi it includes the picture attached. Similar to the issues other users have experienced, there is an error between the FPGA VI Reference out of a FPGA invoke method block to a sub-vi. I tried to click on the link to the KB article linked above but it appears it was taken down. How can i solve this issue?