Using CLIP Clocks problem (sbRIO-9606)

[Crowbar]

Tried several times to import CLIP clocks example to sbRIO-9606 traget (LV2013). Used this:

http://zone.ni.com/reference/en-XX/help/371599H-01/lvfpgahelp/fpga_using_clip_clock/

http://zone.ni.com/reference/en-XX/help/371599H-01/lvfpgahelp/fpga_clip_clock_ex_code/

The VHDL itself seems ok and using Component-level IP wizard i can add this CLIP into project. ClkOut80 and ClkOut80P180 appears in a project. The simple BD is below:

To properly map and route new clocks I must provide a component constraint file (ucf) and here is a problem. At least we need to declare a PERIOD. I've tried several approaches (I've included ucf file in synthesis file list):

and they failed:

1) No ucf file usage. The compiler returns an error on routing (can't find PERIOD)

2) Modified form of ucf from CLIP adder example:

NET "%ClipInstancePath%/ClkOut80*" TNM_NET = %ClipInstanceName%ClkOut80;
TIMESPEC TS_%ClipInstanceName%myClkOut80 = TO "%ClipInstanceName%ClkOut80" 12.5 ns;

NET "%ClipInstancePath%/ClkOut80P180*" TNM_NET = %ClipInstanceName%ClkOut80P180;
TIMESPEC TS_%ClipInstanceName%myClkOut80P180 = TO "%ClipInstanceName%ClkOut80P180" 12.5 ns;

 failed on synthesis: 

ERROR:ConstraintSystem:58 - Constraint <NET
"window/theCLIPs/Component_dash_Level_IP_CLIP0/ClkOut80*" TNM_NET =
Component_dash_Level_IPClkOut80;> [toplevel_gen.ucf(3)]: NET
"window/theCLIPs/Component_dash_Level_IP_CLIP0/ClkOut80*" does not match any
design objects.

ERROR:ConstraintSystem:58 - Constraint <NET
"window/theCLIPs/Component_dash_Level_IP_CLIP0/ClkOut80P180*" TNM_NET =
Component_dash_Level_IPClkOut80P180;> [toplevel_gen.ucf(6)]: NET
"window/theCLIPs/Component_dash_Level_IP_CLIP0/ClkOut80P180*" does not match
any design objects.

3) Multiple variations:

a)

NET "ClkOut80" TNM_NET = ClkOut80;
TIMESPEC "TS_ClkOut80" = PERIOD "ClkOut80" 12.5000000000 ns HIGH 50 % ;

NET "ClkOut80P180" TNM_NET = ClkOut80P180;
TIMESPEC "TS_ClkOut80P180" = PERIOD "ClkOut80P180" 12.5000000000 ns HIGH 50 % ;

b)

NET "%ClipInstancePath%/ClkOut80" PERIOD = 12.5000000000 ns HIGH 50 % ;
NET "%ClipInstancePath%/ClkOut80P180" PERIOD = 12.5000000000 ns HIGH 50 % ;

 c)

NET "%ClipInstancePath%/ClkOut80" TNM_NET = %ClipInstanceName%/ClkOut80;
TIMESPEC TS_%ClipInstanceName%myCLIPclk_out80 = PERIOD "%ClipInstanceName%/ClkOut80" 12.5000000000 ns HIGH 50 % ;

NET "%ClipInstancePath%/ClkOut80P180" TNM_NET = %ClipInstanceName%/ClkOut80P180;
TIMESPEC TS_%ClipInstanceName%myCLIPclk_out80P180 = PERIOD "%ClipInstanceName%/ClkOut80P180" 12.5000000000 ns HIGH 50 % ;

 d)

NET "%ClipInstancePath%/ClkOut80*" TNM_NET = %ClipInstanceName%ClkOut80;
TIMESPEC TS_%ClipInstanceName%myClkOut80 = PERIOD "%ClipInstanceName%/ClkOut80" 12.5000000000 ns HIGH 50 % ;

NET "%ClipInstancePath%/ClkOut80P180*" TNM_NET = %ClipInstanceName%ClkOut80P180;
TIMESPEC TS_%ClipInstanceName%myClkOut80P180 = PERIOD "%ClipInstanceName%/ClkOut80P180" 12.5000000000 ns HIGH 50 % ;

they will all return the same type of error (see above) 

Question: what constraint file should I include to make example work?

Konstantin

[SchamWow]

Crowbar -

Do you need a constraint file? I was able to compile a VI with your block diagram without the constraint file and the CLIP defined clocks.

See the following .zip file.

Scham

[Crowbar]

Scham, you are right. The projet you've listed and mine (without additional ucf) are working. 

Why I've posted a question. Initially I created this test code for a CLIP:

And it failed to compile with an error: "LabVIEW FPGA:  The compilation failed due to timing violations, but there is no path information because the timing violations are not of type PERIOD." Compilation log in attach. Then I decided to play with additional constraints file in order to remove an error. 

After your post I tested this (working):

And this (not working and returns the same error, note that without DIO node it compiles and works):

Let's sum up:

1) Why and DIO node presense in an SCTL steered by clkout80p180 leads to an error?

As for timing constraint I realize now: the fact is that xilinx tools provide timing information on outputs of DCM automatically based on timing constraint of an input (in our case it is CLK40 and it is known) so we do not need any additional ucf file with PERIOD information