Using Xilinx CoreGen with sbRIO 9606

[orbelsevoyan]

Hello All,

As new sbRIO devices has Spartan 6 LX45 which has 58 DSP cores, it is actual to use thic devices for signal processing, now I am faceing some problem using IP generated by CoreGen as it is totaly different from the one that is being generated for 7965R, for example it dos not have Reset input, clock input is not clearly defined, dose not have some other features also. And here is my question.

1. Is it possible to use FIR IP with 9606 sbRIO devices (dose LV FPGA supports this)?

2. If answer to above question is positive, can you give me some example (step by step will be prefered) to use it.

Software: LV 2011

Hardware: sbRIO 9606

Waiting for your reply.

Orbel Sevoyan

CLA

[Paul-B]

Hello orbelsevoyan,

The IP generated are different because the chip types are different. Can you provide more information about your application. Are you trying to move from the 7965R to the 9606? If you are moving your code from an existing 7965R project to the 9606 sbRIO, you should be able to use FIR IP with the 9606 sbRIO. You will need to remove any old IP blocks from your existing project and drop new ones for the sbRIO.

Paul-B