Using a newer version of Vivado to synthesize IP and then integrate into LabVIEW FPGA

[Terry_ALE]

This is question in concept.  Has anyone developed (or tried to) VHDL/Verilog using a newer version of Vivado than the intended version of LabVIEW FPGA and hardware support?  If so, what were the experiences? 

[Jimmie_A.]

Hi,

You find the compatibility between LabVIEW, Xilinx Compilation Tools and NI FPGA hardware here:
https://www.ni.com/en/support/documentation/compatibility/19/compatibility-between-xilinx-compilatio...

I wouldn’t recommend you trying to use a newer version than the ones we list in the document above.

Why?

We spend a great deal of time testing and verifying all functionality whenever we upgrade to a newer Xilinx tool i.e. run various tests (with or without LabVIEW) to make sure existing functionality works correctly in the new version.