08-28-2025 04:11 PM
My current project runs quite smoothly, (using a cRIO-9053, NI-9215, and NI-9467) with the exception of the NI-9215 waiting approximately 5ms to start taking voltage samples from t0. Sense the wait period is consistent through every test I figure the answer might be straight forward. I have tried several things including changing the 'loop wait timer' from 0ms to 5ms.
08-28-2025 07:50 PM
Please share your FPGA code as well. The issue might be from your FPGA code.
08-28-2025 07:54 PM
Here you go!
08-28-2025 10:14 PM
There is no correlation between NI-9467 and NI-9215 in your current code.
Please refer to the example cRIO data logger with GPS synchronisation and timing
08-29-2025 12:41 AM - edited 08-29-2025 12:42 AM
08-29-2025 12:45 AM
yeah I accidentally removed the loop before taking the screenshot and posting it. With the loop it still has the same problem…
08-29-2025 12:59 AM
Hi wsimpson,
@wsimpson0050 wrote:
yeah I accidentally removed the loop before taking the screenshot and posting it. With the loop it still has the same problem…
This doesn't help to debug your code, especially since you only post images of code!
Additionally you start the FPGA VI just before the while loop in the RT code. Seems senseless to me as you already try to do other stuff with FPGA before…
08-29-2025 01:16 AM
Hi GerdW! Thanks for the feedback! Very helpful! Would you like for me to attach a zip file with the code? If so, please say yes.
Additionally, thanks for pointing out my senseless mistake! As I stated before, the code does what I want, except for the first 5.1ms! My question is why.
08-29-2025 01:24 AM
Hi ZYOng! Thanks I will look at it again. Could you also explain what you mean by “no correlation between NI-9467 and NI-9215 in your current code”.
08-29-2025 01:36 AM
Hi wsimpson,
@wsimpson0050 wrote:
Could you also explain what you mean by “no correlation between NI-9467 and NI-9215 in your current code”.
Because there is no dataflow dependency between the NI9215 and NI9467 loops visible in the image.
There also is no other dependency between those two modules visible in your images…
Do you know the basic LabVIEW mantra of "THINK DATAFLOW!"?
When you want us to debug your code then you should attach code - and not just images of code, even with deleted structures!
As I don't have your hardware I will not be able to run your code: in this case you should follow our advices and change your code to apply common sense and THINK DATAFLOW!