What is the clock rate of NI cRIO controller with Real-Time Processor?

[NAGINENI]

Dear all,

We know the FPGA clock rate is 40 MHz, At what clock rate the VI program is running in the NI cRIO 9039 controller with Real-Time Processor?

These are the specifications available in the manual:

CPU:  Intel Atom E3845

Number of cores: 4

CPU frequency: 1.91 GHz

 If someone knew about the clock rate of NI cRIO real-time processor, please let me know.

Thanks and regards

Sukumar

[GerdW]

Hi Sukumar,

why do you need to know the RT CPU clock frequency?

(From the spec sheet you already know the 1.91GHz…)

[NAGINENI]

Hello GerdW,

If we generally use an FPGA clock rate of 40 MHz, the VI is running in the time of 25 nanoseconds. In case, if I am executing a VI program in the cRIO RT (Real-Time) environment, how much maximum time it will take to running the VI program. 

why do you need to know the RT CPU clock frequency?

We are having the problem of delay in an output image display while running an image processing algorithm in the cRIO RT environment. So that we need to know the clock rate, it's required for the performing iteration in the loop.

Thanks and regards

Sukumar

[GerdW]

Hi Nagineni,

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@NAGINENI wrote:

If we generally use an FPGA clock rate of 40 MHz, the VI is running in the time of 25 nanoseconds.

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Well, 25ns is "one clock cycle" - and not all operations are executed within one clock cycle in the FPGA. Image processing will surely take more than just one cycle…

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@NAGINENI wrote:

In case, if I am executing a VI program in the cRIO RT (Real-Time) environment, how much maximum time it will take to running the VI program. 

---

You can measure the time it takes by reading a timestamp before and after the (sub)VI.

When the algorithm is "RT friendly" execution time will not differ that much - as that's the promise of RT systems!

(When you use functions being "not RT friendly" like memory (de)allocations you need to improve your VI…)

[NAGINENI]

Hello GerdW,

Thank you for the good information. 

@GerdW wrote:

You can measure the time it takes by reading a timestamp before and after the (sub)VI.

I measured the time using a time step, the execution time for that particular sub VI is around 2-4 seconds.

@GerdW wrote:

 25ns is "one clock cycle" - and not all operations are executed within one clock cycle in the FPGA.

As you said 25ns is "one clock cycle" in the FPGA. Similarly, can you give information about the "one clock cycle" in the cRIO RT system?

Thanks and regards

Sukumar

[GerdW]

Hi Nagineni,

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@NAGINENI wrote:

As you said 25ns is "one clock cycle" in the FPGA. Similarly, can you give information about the "one clock cycle" in the cRIO RT system?

---

One clock cycle of that Atom CPU is 1/1.91GHz…

But that number is senseless as the Atom will need more than one cycle per instruction - and is way less determined as is the FPGA!

[crossrulz]

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@GerdW wrote:
One clock cycle of that Atom CPU is 1/1.91GHz…
But that number is senseless as the Atom will need more than one cycle per instruction - and is way less determined as is the FPGA!

---

Due to pipelining, it can average out to 1 cycle per instruction for each core.  But the rest of your point is dead on: RT is meant to be deterministic at the ms level, maybe the 10s or 100s of microseconds.  But you still have the OS and other processes jockeying for CPU time.  So the rest of this discussion is irrevelant just due to the nature of microprocessors running any OS.

[Intaris]

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@NAGINENI wrote:

Dear all,

We know the FPGA clock rate is 40 MHz, At what clock rate the VI program is running in the NI cRIO 9039 controller with Real-Time Processor?

These are the specifications available in the manual:

CPU:  Intel Atom E3845

Number of cores: 4

CPU frequency: 1.91 GHz

 If someone knew about the clock rate of NI cRIO real-time processor, please let me know.

Thanks and regards

Sukumar

---

I think you fundamentally have misunderstood what these clocks mean.

The FPGA portion is completely separate to the RT portion of the hardware. Both need to be programmed individually (typically with completely different portions of the job you're trying to do).

Data is passed between them via DMA FIFOs.

The 40MHz is completely irrelevant to the RT portion of the hardware and the 1.9GHz is completely irrelevant to the FPGA portion of the hardware.

[NAGINENI]

Dear Intaris,

Thank you for your response.

I would like to say that I am not executing my LabVIEW program in the FPGA environment. I am executing my LabVIEW program only in the RT (Real-Time) Processor. 

(Embedded compact RIO controller with the Real-Time processor and Reconfigurable FPGA)

@As I mentioned in the replay,

If we generally use an FPGA clock rate of 40 MHz, the developed LabVIEW program is running in the time of 25 nanoseconds (one-clock cycle). In case, if I am executing my LabVIEW VI program in the cRIO RT (Real-Time) environment, how much maximum time (one-clock cycle) it will take to running the VI program.

[GerdW · Accepted solution]

Hi Nagineni,

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@NAGINENI wrote:

I would like to say that I am not executing my LabVIEW program in the FPGA environment. I am executing my LabVIEW program only in the RT (Real-Time) Processor. 

@As I mentioned in the replay,

If we generally use an FPGA clock rate of 40 MHz, the developed LabVIEW program is running in the time of 25 nanoseconds (one-clock cycle). In case, if I am executing my LabVIEW VI program in the cRIO RT (Real-Time) environment, how much maximum time (one-clock cycle) it will take to running the VI program.

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You don't run your VI in the FPGA, so any question about 40MHz clock in FPGA is irrelevant (aka senseless).

(Even when you use the FPGA the VI will most likely need more than one clock cycle so it will not run within one clock cycle! And even on FPGA you could measure how long the VI will need for execution!)

When running the VI in the RT environment any "clock cycle counting" is irrelevant (aka senseless) as you run in a (more or less) standard OS environment on a (more or less) standard CPU. Use timing functions to measure how long the VI needs for execution!