What is the maximum number of the parallel blocks or maximum pair of shift register used in FPGA VI time loop with cRIO 9104?

[TCPIP]

  I am writing a FPGA VI with module cRIO 9104, I need to do a lot of parallel execution of inside a timed loop. In total, I have used 20 pairs of shift registers in the timed loop, which simply means there is 20 parallel exceution across ONE time loop. However, it tells me that there is an over-used of the FPGA resources in the compliation report. One is the Slices and the other is the number 4 of LUTS ( see the attached file), would the compile will be sucessful if I change it to ALL block diagrams cascaded in series without using any shift register accross the timed loop? And do you think that it is reaosnable to have 20 pairs of shift register arranged in parallel inside a timed loop.

  Thank you!

[RyanB]

Your compilation report has 2 useful numbers to help answer your question, I'll summarize:

Number of Slice Flip Flops = 27%

Number of 4 Input LUT's = 100% *

You are using the Timed Loop Shift registers to pass a value from one iteration of your loop to the next.  The LabVIEW FPGA compiler will use Slice Flip Flops to create this behavior in the FPGA fabric.  You are only using 27% of the Flip Flops, therefore the 20 Shift Registers are not your problem. 

LUT's (Look Up Tables), which are the basic logic building block of an FPGA, are your problem.  You are using over 100% of the LUT's in this FPGA.  To fit in this FPGA you will have to reduce the amount of logic (and/or gates, additions, comparisons, etc.) in your design.

-RB