Hi Jhun,
 
@JHUN-KULI wrote:
What I mean by changing the sampling rate here is that when the program is not running, the input value of the sampling rate of THE RT terminal is changed, and then the VI of RT is run. At this time, the RT terminal will load the parameter data into FPGA before data collection. When I stop running rt. vi, re-enter a new sampling rate and run rt. vi again, at this time, 9232 still collects data at the maximum sampling rate.
You just "Run" the FPGA VI in your RT VI. Typically when the FPGA VI already is running it will not get restarted by calling the "Run" method again!
Solutions:
- abort and run the FPGA VI correctly in the RT VI
- when parameters should be changed in the FPGA VI you should place the code to handle those changes inside the main loop(s) of the FPGA code…
	Best regards,
GerdW

 
  
 using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019