Why is "FPGA device emulator" not an option in my target list?

[Kjell-E]

I have the LabVIEW RT module and the FPGA module installed.
(LabVIEW 7.1)

I have developed several VI's for the cRIO, but one thing has always stumped me: On my targets list, I have "Windows", then I have "compile only xxxx" where xxxx is my FPGA device, then I have "RT:IP-address" and also "VISA::FPGA" option, but, as mentioned in the topic, I do not have a "emulator" option in the target list.

Now, up until today, that has not been to much of a problem, but now, I have a bug in my VHDL code, and since I cant emulate, I cant use probes and every change I make forces me to do a 30+ minute re-compilation. To make it worse, I do not have enough room left on my device to have "Indicators" for all signals I would like to look at, so debugging my code is -A PAIN-.

If anyone could help me with tips as to how to get the "emulator" option, I would be grateful.

System specs:
Win XP home (SP2 with all the latest updates)
LabVIEW 7.1
LabVIEW RT ETS
LabVIEW FPGA (1.1?)
Pentium 4, 1.6GHz
768MB RAM.

[Ricardo_SR]

Hello,

The emulation target is only available if you have a R series board (NI 7831, 7811, etc) not with cRIO.  When you install these boards, the option for the emulator should appear.

Since you don't have this option right now, what I would suggest is to target to Windows and open your FPGA VI.  That will give you an idea and will help you troubleshoot your VI.

Hope this helps.

Ricardo S.

National Instruments

[Kjell-E]

Thanks!

This seems to work reasonably for the time beeing. My biggest problem is that when I read the Digital output module (to software verify what it outputs), I get random results, even though I explicitly write to the output first. This, I hope, is just a feature of having the target as windows!

[Ricardo_SR]

Hello,

I am glad that targeting LabVIEW for Windows does the trick.  About the Digital Input, you are right.  All IO is simulated when targeting LabVIEW for Windows. So what you get is only random data generated by LabVIEW.  As soon as you target to the FPGA, it will talk to the IO and then you will have true data.

Ricardo S.

National Instruments.