Peter,
We currently have not announced any larger FPGA's, however I cannot comment on any ongoing internal projects. However, rest assured there are always good things in the pipeline.
😃 We do recognize there is a demand for higher-gate count FPGAs. In the meantime, there are a number of things you can do to signifcantly reduce gate usage such as reducing array usage, minimizing front panel controls/indicators, and avoiding use of expensive functions like divide and array functions. Also, if your calculations aren't running all the time, you may consider swapping bitfiles on the FPGA programmatically from the host (ie have one bitfile for one portion of a test, and download another bitfile for another test).
Some links that may be useful:
How Do I Change the FPGA Compiler to Optimize for Area or Speed?
http://digital.ni.com/public.nsf/websearch/EE940C191DDCE9CE86256E5500783A4D?OpenDocument
How Can I Optimize/Reduce FPGA Resource Usage?
http://digital.ni.com/public.nsf/websearch/311C18E2D635FA338625714700664816?OpenDocumentMessage Edited by Paul M. on 08-11-2006 12:12 PM
--Paul Mandeltort
Automotive and Industrial Communications Product Marketing