Xilinx FFT IP 7.1 (Handshaking 4-wire equivalent)

[jblee]

Hi all,

I'm trying to figure out how to get the Xilinx FFT 7.1 IP to handshake properly like the 4-wire LabVIEW FPGA FFT Express VI. I need to the use Xilinx FFT due to the 8192 maximum length constraint on the express vi.

The common 4-wires for handshaking are:

INPUT: input valid

INPUT: ready for output

OUTPUT: output valid

OUTPUT: ready for input

The Xilinx has a few pins which are similar such as

OUTPUT: data valid

OUTPUT: ready for data

OUTPUT: done/edone

INPUT: Clock enable?

Any ideas on which pins I can use as the INPUTS: input valid and ready for output?

Thanks a bunch

[Dave.C]

Hi Jblee,

Couple of questions...

Could you provide us with your version of LabVIEW, and the hardware your working with?

For clarification, when you ask about the Xilinx pins, are you referring to the pins listed in Table 1 of the Product Specification document for LogiCORE IP Fast Fourier Transform v7.1?  More specifically, are you asking if the IP supports 4 wire handshaking and if so, what pins are used to implement it on the Xilinx FFT IP?

It may be something Xilinx has more information on too so I'd encourage you to check some of their other resources as well.

It sounds like you're familiar with handshaking in LabVIEW but this Community Example might be a good resource anyway.  It provides a general overview of the topic.

Thanks,

[jblee]

Hi Dave,

I am indeed referring to the pins listed in the LogiCORE IP FFT v7.1 you linked to and yes, I want to know how to use those pins to do 4-wire handshaking. I've had some experience doing some 4-wire handshaking with the FFT Express VI and high throughput math but never with sclr, ce, etc.. signals.

Thanks

The hardware/software:
FlexRIO 7966R

LabVIEW 2011 SP1

[Dave.C · Accepted solution]

Hi Jeffrey,

I've attached an image I hope you'll find helpful.

Input valid is going to correspond to the clock enable (ce) pin

Output valid with data valid (dv) and

ready for input with ready for data (rfd)

Let us know if you have more questions.

Thanks,

[PatrickR]

This is an older post, but I think there is something incorrect so I'm bring replying to it instead of starting a new post.  I don't believe the clock enable (CE) acts the same as an 'Input Valid' in the 4-wire handshake.   The CE pin freezes the entire state of the FFT pipeline, so the equivalent of Output Valid ('Data Valid' or 'dv') will not become true if the CE pin is not asserted (or perhaps it will freeze in the state it was in the last time the CE pin was asserted? )

I have actually tried wiring the CE pin, and it I wire something else besides a 'T' constant, it will cause the entire diagram to not execute if it is false.   If the state of the CE pin depends on for example, the timeout state of a FIFO, then entire diagram will never advance past an initial state.    I think this is because LabView will automatically wire the CE pin, unless you tell it not to in the 'IP terminals' section under the 'Configure...' local menu.    If you don't map the CE pin, you get the following warning:

Warning: No port in the IP maps to the clock enable signal. If the IP is sequential, this situation produces inconsistent results between simulation and actual FPGA hardware execution. When emulating on a development computer, the IP executes only when the containing block diagram structure executes. When executing on an FPGA target, the IP always clocks in input values regardless of its place on the block diagram. If you place sequential IP in a Case structure, LabVIEW returns an error when you attempt to compile the FPGA VI.
To address this issue, ensure sequential IP has a clock enable port. Then, use this page to map this clock enable port to a clock enable signal.

But I think this is the behavior you want if you want it to behave somewhat like an 'Input Valid'  (although you will need additional logic to assert the CE pin if there is no input but you need to read the output.   I am testing this behavior now