Xilinx IP - how configure the clock for the IP

[heel]

Am I right in selecting "No Clock"?

In an FPGA, where I want to implement a Decimating FIR filter using Xilinx FIR Compiler v7.2. (LV20 SP1/32).The filter will run in a single cycle timing loop.

In the Xilinx FIR Compiler v7.2 there are 3 options to select the clock: ["No Clock", aclk, s_axis_data_tvalid].

Because selecting any other but "No Clock" would give a Boolean input which I would not know what to connect to as the clock is not exposed in LabVIEW.

One could select aclk and hide it but here I am guessing, and selecting "NoClock" seems not to work either...

So I am stuck - any hints are appreciated.

[heel]

Ok - figured out by trial and error that one must select aclk as clock source. 

It is a mystery to me what use the "No Clock" option has - a FIR filter without a clock makes no sense to me.

Anyway I discovered a solution.

[Terry_ALE]

In all cases we have used aclk with the Xilinx FIR.  The interface where you set this is part of the LabVIEW FPGA IP Integration Node, see https://zone.ni.com/reference/en-XX/help/371599P-01/lvfpgadialog/ipi_clock_enable/

This interface is used for non filter use cases as well.

[heel]

ok thanks Terry,

You link to IP integration node. 

I am though a bit confused if the following is incorrect:

For the LV builtin xilinx IP tool (below picture) there is no need to use the IP integration block. Right?

[Terry_ALE]

When calling the Xilinx IP items, they pull in the (Xilinx) IP using the IP Integration Node.  So sometimes the answer to questions about the Xilinx IP functions can be found by checking the help of the IP Integration Node.

When using the Xilinx IP you do not need to use the IP Integration Node.