atan2 in fixed point FPGA

[Daaan]

I'm using the atan2(x,y) function implemented on an FPGA (NI-7851R) and have a simple question that's frustrating me.

See the attached vi, my two inputs (x,y) are fixed point numbers, 16-bit word length, 1-bit integer (ie, -1.000000, 0.9999695 with 3.051758e-5 precision).

Since the atan2 value has to be between -pi and pi, and labview ouputs in pi radians (rather than just plain radians), i would expect the output to be the same format as the input, a 16-bit number between -1 and 0.9999695 (3.051758e-5 precision) with only 1-bit used for the integer.

Instead, the VI forces it to be a 16-bit word but with 2-bit integer part (ie, -2.0000, 1.999939 with 6.1036e-5 precision, see attached picture atan2_output_type.png). This gains me nothing and I only get half the precision I should have! I've tried several possible inputs and I've confirmed it only returns numbers between -1 and 0.9999389 (6.1036e-5 precision).

I can't seem to be able to change it since all the options in the dialogue box are grayed out (see attached picture atan2_dialogue.png), like it has decided that is what it should return given my inputs. Can anyone explain why it is doing this? Is there something simple I am missing? I'd need that extra bit to go on the decimal, not the integer side of my fixed point number.

Thanks,

Dan

[JLewis · Accepted solution]

Hi Dan,

Normally a bit growth like that is due to a corner case, in this case I would assume it needs to cover 1.0 pi radians as a possible output. If you need more output precision, just increase the word length; with a fixed integer word length, all bits you add will be fractional. If you don't want the extra integer bit, just discard it by using To Fixed-Point to set the integer word length to 1, and set the overflow mode to Wrap.

Jim

[Daaan]

Perfect, as you said i increased the output bits to 18 to get my precision back and then did To Fixed to truncate back to 16. I naiively hadn't realised you could do this since it's a 16-bit FPGA... This means FPGA code can handle "internal" numbers that are greater than 16-bit? First time I've used an FPGA target so this is all new.

Thanks Jim.

[JLewis]

That's great, FPGAs are definitely a different world! There is not really a concept of native word length on FPGAs, as more bits just mean more logic slices in most cases. Exceptions are Block RAM and built-in multipliers, which do have set limits. LabVIEW will take care of implementing any size up to 64 bits, though; it's just good to be aware of what the "sweet spots" are for built-in operations (e.g. 18x25 is the signed multiplier size for all the newer targets).

Jim