cRIO 9074 Hybrid Mode

[S1ack]

Project was using scan engine exclusively: At Total CPU utilization on the cRIO 9074 was @ about 61%.

I had to move one module to the FPGA target to do RMS current calculations on six channels within a 9205. This data is passed to the host VIs via User Defined I/O Variables.  (32 Total, 6 are the RMS outputs, the remainder are the 26 channels sent straight into FXP variables) So 32 total USer Defined I/O Variables.

FPGA VI works as expected and verified when deployed from development.

I sent the bit file to flash and set the target to run the VI on power up. - It does.

Next I transfer the host VI project to the 9074 target.

And although it runs the processor is pegging at 99-100% and I get intermittent warnings about waiting for the target to respond.

As I mentioned, before I integrated the FGPA outputs into the project, the Total Utilization was ~61%. The only changes to the host VI project was replacing the module variables that were formerly DBLs from the scan engine, to the FXPs that are from the FGPA.

What I am curious about is how does running in hybrid mode effect Timed Loops that were/are tied to integer multiple of the scan engine? I have several of these.

As I understanding running in Hybrid mode has the FGPA compiler add scan engine code for all the modules that still reside under the cRIO target in the project tree.

I would have expected zero net change to my CPU after doing this.

[Ben-N]

Hi S1ack,

Running a CompactRIO in hybrid mode requires a fair amount of resource overhead, but most of that overhead is related to the FPGA.  I'm surprised you saw that much of a jump in CPU utilization, but I'm not totally caught off guard that it increased some.  It sounds like your FPGA code is working just fine also, but that won't have any impact on CPU utilization.  There are a few things that would help clafify what exactly happened.

How are you getting your values back from your FPGA to your RT code?  Are you using a Read/Write Control Method or a DMA FIFO?  If you are using a Read/Write control, do you have all 32 variables being read as part of the same node?  Is this node in a timed loop, and if so, how fast is that timed loop running?  Has this rate changed since you were running in Scan Mode?  With your processor perioidically railing, are your timed loops finishing late at all?  I'm just trying to see if the cause of this issue is the timed loops or something else.  Also, is there anything at all that you changed since moving to Hybrid mode?  What other hardware is in your chassis? 

[S1ack]

Thanks for the reply.

I fixed the issue, by adding FPGA interface code into my host vi. Prior to this, I was setting the FPGA to run always, and the host vi was interfacing solely with user defined i/o variables from the FPGA. Now I open a reference to the FPGA bit file, invoke the download method, invoke the run method. Since doing this the whole project now successfully runs as startup, and my CPU % Total is unchanged from deploying interactively from the development environment.

Answers...

How are you getting your values back from your FPGA to your RT code?: User Defined I/O Variables. This was suggested by a NI systems engineer - possibly because it was easiest, and he knows I am relatively new to Labview and cRIO. If there are more efficient methods, I would like to try them out. I am attempting to move more functionality onto the FPGA to recover some host CPU, and my compiles are failing..Sometimes due to size, sometimes due to timing.

Are you using a Read/Write Control Method or a DMA FIFO? No, user defined i.o variables.

If you are using a Read/Write control, do you have all 32 variables being read as part of the same node?  32 User defined i/o variables (FPGA to Host).

Is this node in a timed loop, and if so, how fast is that timed loop running?  Doesn't really apply, but my I/O variables are referenced throughout the host VIs, sometimes in timed loops tied to scan engine (or multiples thereof) and sometimes in timed loops tied to the 1khz timing source.

Has this rate changed since you were running in Scan Mode? Scan engine time for those modules has been unchanged during the course of my FPGA development.

With your processor perioidically railing, are your timed loops finishing late at all?  I never investigated this, and now as I have a working solution, may not re-visit this.

Also, is there anything at all that you changed since moving to Hybrid mode? No. Project was exclusively scan engine only. I knew from the beginning that I would eventually have to move one module to FPGA, as the RMS calculations had to be done quickly enough to catch harmonics and switching noise.

What other hardware is in your chassis? 

2 16 Channel Thermocouple modules (9213 I think)

2 32 Channel Digital Input

1 32 Channel Digital Out

And 1 32 Channel Analog Input - the 9205 that I created the custom FPGA code for six of those channels.