Rif.: cRIO - Best approach to acquire and generate with different modules at different frequencies

[aRCo]

Hi,

i'm working with a cRIO consisting in 6 different C modules. For the moment i'll focus on the acquisition. The worst case sees:

Acquisition:

- NI9205: 16 AI ch @ 150kHz

- NI9401: 4 DI ch @ 1MHz

- NI9203: 8 AI ch @ 50kHz

- NI9219: 4 AI ch @ 1Hz

- NI9375: 16 DI ch @ 50kHz

Briefly, i'm wondering which is the best way to implement the FPGA code in order to acquire all the channels maintaining the specified rate and to pass the acquired data to the RT code. Consider that the DMA FIFOs availabe are only three.

Thanks,

aRCo

[LiciaP]

Hi aRCo,

a suitable approach could consist in acquiring each module in a separate parallel loop, in order to set different indipendent sample rates.

Then you can transfer data through a FIFO to another parallel loop which will interleave data and write them to one or more DMA FIFO. Host VI will de-interleave data read from the FIFO based on how the array was created in the FPGA VI.

I hope this helps!

Bye,

Licia

[aRCo]

Thanks for answering.

Another delicate question is the one related to the data types. Considering that i'm going to use a single U32 DMA FIFO, i need to convert all the acquired data types to the U32 one.

The conversions to realize are:

- NI9205: 16 AI I16 ch to 8 U32 elements

- NI9401: 4 DI BOOL ch to 1 U32 element

- NI9203: 8 AI FXP ch to 8 U32 elements

- NI9219: 4 AI FXP ch to 4 U32 elements

- NI9375: 16 DI BOOL ch to 1 U32 element

Can you please show how to up-convert (in FPGA VI, to U32) and down-convert (in RT VI, from U32)?

[LiciaP]

Hi,

you can refer to the following examples:

- Passing, Converting, and Graphing Analog Data Through a U32 FPGA FIFO

- High Speed 32-Channel Binary Data Logging with DMA Data Transfers, NI 9205 Module

- How Can I Transfer My Fixed-Point Data Using a FIFO in LabVIEW?

I hope it helps!

Bye,

Licia