07-27-2023 06:49 AM
cRIO9039, server does not respond when compiling FPGA program。 When it compiles on another computer, everything works fine. What is the error that prevents compilation.
“NI-Farm: Farm server is not responding. Be sure the specified hostname is correct, the server is running and configured to accept remote requests.”
07-30-2023 09:37 AM
I'm sorry that I overlooked this message. I haven't done much with cRIOs, but do have experience with systems running LabVIEW Real-Time on target processors, including PXI and sbRIO platforms.
Your cRIO is running LabVIEW Real-Time. To develop code on the cRIO, you (probably) connect it to a PC running LabVIEW with the Real-Time Module installed, and develop using what I'll call a LabVIEW Real-Time Project, with a Host section (which might have not much code, particularly if you intend to run the Real-Time system "headless", without a connection to a PC "Host") and a (Real-Time) Target section (which runs on the cRIO). This R.eal-Time Project, in its "Target" section, shows the LabVIEW code that will be deployed to the cRIO and configured to run on the cRIO when it starts. The actual "LabVIEW Code" (meaning files with the extension .vi, .ctl, etc.) all live on the PC as part of the Real-Time Project. Similarly, the FPGA code (shown in the Project as in the "Target" section, in a folder called FPGA) also lives on the PC. When you deploy your code to the cRIO (from your PC), all of the executable code gets shoved down the Ethernet connection between your PC and your cRIO and saved on the cRIO. I believe (but am certain this is correct) that the FPGA bitfile code also gets moved to the cRIO, and potentially written to the FPGA (this might also be done when the RT side "starts up" the FPGA).
So if you attempt to compile the FPGA code from the cRIO, you will fail, as (a) the cRIO doesn't have the FPGA "source" code (which is living on the PC as part of the RT Project), (b) the cRIO doesn't have the URL of the FPGA "Server Farm", and (c) the cRIO doesn't have the appropriate "logon credentials" needed to sign in to the Server Farm.
So the solution is simple. Open the Project on your PC. Navigate to the Target section of the Project and find the FPGA code. Compile it. Get a working BitFile. Find the VI in the Target where you start the FPGA using Open FPGA Reference. Make sure it links to your FPGA VI or BitFile. Finally, connect the cRIO to the Host machine and deploy the RT Code to the cRIO (you may want to make it auto-start when you configure the Deployment).
Bob Schor
07-30-2023 07:50 PM
Thank you very much for the detailed explanation and the solution given. I agree with your explanation about the process of compiling and passing FPGA code between the PC and cRIO. I don't know exactly how they work, but after querying, I roughly understand how they work. The FPGA compiler is installed on the PC side, but the compiler is based on Linux, so although the compilation on the PC side also needs to communicate through the TCP/IP protocol, the main problem encountered is that Labview cannot communicate with the compiler through TCP/IP. Firewalls and other causes have already been investigated.
Finally, I applied for an NI Cloud Compiler account to temporarily solve this problem through cloud compilation. But local compilation still fails to complete.