case structure on FPGA

[Laurent80]

Hello,

I'm now programming some VI for the FPGA 7831R (with LabVIEW FPGA module). Depending on the current time, I would like to execute different parts of code. For example, if 0<Time< T1 or if T1<Time<T2, the application will execute different operations. T1 and T2 are user-defined and past by the host VI to the FPGA VI.

At the beginning I thought I could manage it using some case structure. But it seems that it is not possible to specify some ranges with variable extremities, like "0..T1" or "T1..T2", in the case selector label. And the value of T1 and T2 are variable, and not defined in the FPGA VI.

Does somebody know something about this, or have an alternativ solution to solve this problem ?

Thank you in advance,

[EdDickens]

Your problem is that FPGA devices do not support the String data type. So there's no way to specify a Case as "0..T1".

You can specify a range for a Case using numbers. So you're going to have to specify your time ranges as numerics with no text.

Ed

[Laurent80]

Thank you Ed for the explanation !