Hello,
It is not possible to divide the clock to any arbitrary number. I have attached the clocking scheme for the 5640R.
The 20 MHz Configuration_Clk is not synchronized to the VCXO and runs independently of other clocks. The role of the 20 MHz Configuration_Clk is to provide a fixed frequency configuration
clock that is also used by the I-STC2 ASIC for PCI DMA operations. The Device Reference Clock can be configured as the internal 200 MHz CXO or an external clock provided at the device front panel CLK IN
connector. Specify the device reference clock source by calling the i5640R Configure Timebase VI. The valid values for CDC 7005 divisors (N0...N4) is 1, 2, 4, 8, and 16.
Regards,
Denver
AE, NI India
