combinatorial logic in NI FPGA?

[RichC41]

Is there any way to instantiate un-clocked logic using NI FPGA?  Specifically what I'm trying to do is programmatically connect one port of a FlexRIO Adapter Module (FAM) to another port on the FAM programmatically to create a software-configurable mux.  I want to do it in a way where the logic is unclocked though, e.g. forward that signal without bringing it into a timed loop and having the signal passed through a flipflop in any way.  

EDIT: I want to be clear on why I want to do this.  Let's say my FlexRIO core clock is 100MHz, meaning every flip-flop in the design will be sampling at 100MHz.  I have a signal that's coming in to a FlexRIO via an NI6583 FAM that's toggling at a 40MHz rate.  I want to be able to use that signal in my design but also tee it off and forward the same signal back to an output port unchanged.  If I do this combinatorially I'll get a little bit of phase offset due to routing, but if I bring this in to a single cycle timed loop I'm worried LabVIEW will try to re-clock the signal and push it back out sampled at 100MHz.  Since there's no way for a 100MHz clock to generate a 40MHz signal without a PLL, my clock output rate will be messed up.  Changing my core clock to be integer-divisible of this input signal is not an option due to other aspects of my design.

[wiebe@CARYA]

AFAIK, you can make the FlexRIO run at 40 MHz or 80 MHz. This is probably done with a multiplexer and a divider (e.g. 100X2/5). The model I had could in fact only run up to 80 MHz... 

As far as the routing, I think you'll have to read all inputs, put it in either an array or memory, then output the data using different indices.

I would worry about latency. Those FlexRIOs have buffers. Cable length can be significant. With a 1 meter cable, we got 75 ns latency on the input. So for input\output I'd expect maybe up to 200 ns latency (cable in, input buffers, read\relay\write, output buffers, cable out).

I'd also be worried about clock differences between the FlexRIO and the device. If the clocks are not synchronized, they will drift. 40 MHz on one device will be actually 39.999 or 40.001 MHz. You'd have to sample a lot higher or synchronize the clocks to resolve this.  

[James_McN]

On the FPGA IO nodes you can disable the registers.

I think if you were to put both IO nodes in a SCTL and disable both of their respective registers you might get something like this. But you will need to make sure you are sampling the signal properly through a register for your other logic.

This isn't really the intended usage in LabVIEW so that is why I can't remember for sure that it is able to do so. It will probably also break other rules for example, it will start even if your SCTL isn't supposed to be running in LabVIEW

The other option, depending on your level of comfort with VHDL would be to create a custom CLIP interface for the module which does this internally. The CLIPs that ship with the digital modules are generally fairly simple and not too bad to modify. Assuming it is a permanent case I would probably prefer this route.