crio multiple fpga vi

[BillMe]

The answer to your question is yes. Just remember to open the multiple FPGA VI references (same reference just from different areas of your host app) with OPEN and not OPEN AND RESET (which seems to be the default). And be careful when you say simultaneous...it's not TRUE simultaneous I/O...

[mrak1]

What clock speed are you attempting to attain?  If there is a section of your code that you need to execute at a higher speed, you can possibly locate some of you code into a Single Cycle Timed Loop and set its clock domain.  In addition, you can use a technique like pipelining your FPGA code which "can" help you attain faster clock speeds.  Just remember ==> multiple parallel and independent loops ( hence messy code) in the FPGA program are your friend!

Good luck,

Mike

[P. Jack]

Actually, I am using SCTL as structures for my VIs. I am an HDL (Verilog, VHDL) guy. I am assuming that when I use SCTL, I am using "always" block.

I have another question. In Verilog, when I used unsized integers, the compiler/synthesizer discards unused bits. Is LabVIEW FPGA doing that? Example, I am using a U32 shift register and only the bits 3 to 0 are consistently being used in the VI. Does LabVIEW discard bits 31 to 4 to saved resources?

[mrak1]

Hi,

Unfortunately, I do not recall the ALWAYS Block in Verilog ( it has been many years since I did verilog).  However, if that block represents a block of code that propogates with every tick of the clock, then that is partially correct.  As long as the SCTL is actively executing, it will execute all of the contained combination logic within every tick.  However, you can also exit this loop structure with the stop terminal and re-start it.  There are a few additional ticks that occur on the entry and exit of this structure if you are concerned about timing.

With regards to your other question, the answer is no.  If you would like to conserve the resource on this shift register, store the bits as an array of booleans with 4 elements.  You can always convert the array of booleans to a number to perform operations and then back to an array of boolean ( these operations are free operations that require no FPGA space) Otherwise, LabVIEW will have no way of knowing that the other bits will never be used.

On a side note, I know that you probably have read that arrays on FPGAs are a no-no which is very true if the combined size of the elements in the array are more than 32 data bits wide. 

For example

• 32 element boolean array => ok and only takes up the same amount as a U32
• 4 element U8 array => same
• 33 element boolean array => bad => takes up nearly twice the FPGA real estate for every bit as does the 32 element boolean array
• 2 element U16 array => ok
• 3 element U16 array => bad

I hope that this helps,

Mike