error -61017 in the RT VI

[TCPIP]

  I have successfully compiled the FPGA VI and use the RT to run the FPGA VI for a few times ( by using"Open FPGA VI Reference) , I am also sure that I did not make any amendment of the code, but today, when I use the RT VI to run the FPGA VI, it has a error of -61017, I have compiled it again for a few times and I found that after I run the FPGA VI by RT VI a few times, such FPGA always have such error, does it mean my FPGA VI have problmes?  It takes 2 hours to compile the FPGA VI, so I don't want to always compile it.

  And then, I suppose my RT (hardware) has problems, when I run the RT VI, it spends a lot of time to do the deployment (sometimes 5 minutes). And even I open the RT VI in the LV project, I also need to wait a long time for the PC to display the code. Does my RT have problem?

[Christian Mergl]

Hey,

Which version of LV do you use?

Christian

[TCPIP]

I am using LV 8.2 with the NI RIO 9004 with CRIO 9104 FPGA

[JMota]

To avoid error -61017, I would recommend you use the Open FPGA Reference node in bitfile mode instead of FPGA VI mode. You do this by right-clicking the node and choosing "Select bitfile". This way LV FPGA does not check whether the FPGA VI is up to date with the compiled bitfile; you just need to remember to recompile your FPGA VI once you make a change to it. You should be able to find more information about this option in LV's documentation.

Regarding the RT VI (Host FPGA VI) taking a long time to display, that sounds normal to me, and it is independent of the RT target. I wouldn't worry about it, and just be patient; a faster computer could make difference though.

Hope this helps.

JMota

[Christian Mergl]

Hey TCP/IP,

Is the VI saved on a network drive and did you move the bitfile manually?

Open the bitfile instead of the VI could be a workarround but its no good solution in the long run. So maybe we can find the reason of the error!

Christian

[Juan G]

As JMota stated, If you are haven't made any changes to the FPGA VI or Project that require a re-compile, you can set the Open FPGA Refence node of your Host VI to point to the bitfile instead of the FPGA VI. That should bypass any error check as to whether the VI needs to be recompiled or not.

This error was common in LabVIEW 7.1 but since you have a LaBVIEW version 8.x, it may vary from case to case.

Regards,