error 61017 on LV 8.2

[UT_Terp]

I had been running a host VI on our laptop with no problems for 2 days, making no changes. Then, when I tried to run it this morning I get error 61017, even after compiling. The same error comes up after reset of the cRIO and restarting the laptop. Any ideas, thanks

[JMota]

I don't have an answer to your problem, but can tell you of a way to tell whether an FPGA VI needs to be recompiled or not (in case you didn't know about). From the LV Project right-click the FPGA VI and select "Target-Specific Properties...". This will bring up a dialog telling you the information about the last compile and whether a new compile is necessary before running the VI.

If you are confident that you haven't made any changes to the FPGA VI or Project that require a re-compile, you can set the Open FPGA Refence node of your Host VI to point to the bitfile instead of the FPGA VI. That should bypass any error check as to whether the VI needs to be recompiled or not.

Hope it helps.

JMota