LabVIEW
fpga : DMA FIFO arbitration
Hi !
In my FPGA (currently using a 7813R board), two loops (and more in the future) are running in parallel, executing the same code (attached in this VI) and writing data in the same DMA FIFO. It happens sometimes that requestors will try to write in the queue at the same time, that's why this FIFO is set as "always arbitrate".
Data written by the first accessor is correct. But data written by the second requestor is shifted one bit on the left : for example instead of reading Ox55 in the host VI, I read OxAA...
Is it a problem of arbitration ? or is my code wrong ?
Thanks !
In my FPGA (currently using a 7813R board), two loops (and more in the future) are running in parallel, executing the same code (attached in this VI) and writing data in the same DMA FIFO. It happens sometimes that requestors will try to write in the queue at the same time, that's why this FIFO is set as "always arbitrate".
Data written by the first accessor is correct. But data written by the second requestor is shifted one bit on the left : for example instead of reading Ox55 in the host VI, I read OxAA...
Is it a problem of arbitration ? or is my code wrong ?
Thanks !
In fact it looks like only the first 16 bits are written and one-bit-left-shifted of the data of the 2nd accessor are written...
Weird !
Message Edité par zyl7 le 06-24-2008 04:45 AM
Weird !
Message Edité par zyl7 le 06-24-2008 04:45 AM
I think I have an beginning of explaination about the weird behaviour of the system...
=> I'm using my FPGA that way : I output a signal on one pin which directly wired to an input and i'm reading the states arriving on that input.
=> It looks like I receive uncorrupted data on the line being watched by my oscilloscope ! The other line, which is directly linked by a wire, returns corrupted data !
Why my oscilloscope has an influence on the data ? The input of my oscilloscope is set to 1MOhm, so it shouldn't disturb/help in any case the states arriving at the inputs of my FPGA...
=> I'm using my FPGA that way : I output a signal on one pin which directly wired to an input and i'm reading the states arriving on that input.
=> It looks like I receive uncorrupted data on the line being watched by my oscilloscope ! The other line, which is directly linked by a wire, returns corrupted data !
Why my oscilloscope has an influence on the data ? The input of my oscilloscope is set to 1MOhm, so it shouldn't disturb/help in any case the states arriving at the inputs of my FPGA...
Hi,
yes I still have the problem, but I now know why. At FPGA start, my outputs are in high impedance. And in my application i'm looking at egdes... so the first edge is never detected because the loop scrutating my inputs doesn't see a false-to-true egde but a high-impedance(voltage unknown)-to-true transition.... My temporary solution is to add a pull-down resistor on my inputs...
yes I still have the problem, but I now know why. At FPGA start, my outputs are in high impedance. And in my application i'm looking at egdes... so the first edge is never detected because the loop scrutating my inputs doesn't see a false-to-true egde but a high-impedance(voltage unknown)-to-true transition.... My temporary solution is to add a pull-down resistor on my inputs...
