fpga DMA FIFO compilation error

[bogdan_ETH]

Hello,

I have a cRIO 9074 with FPGA. I am trying a simple piece of code to learn how to aquire data that is generated on the FPGA at a rate of 10 KHz and transfer it to the Host VI for processing it later offline. However, I encounter this compilation error when compiling this basic FPGA VI containing a FIFO write node (picture of the VI attached below). In the Compilation Report, it says that there were 256 Block RAMs used (the total number is 40), therefore an error was produced. The exact compilation error notification from the Xilinx report is reproduced below:

# Starting program map

# map -o toplevel_gen_map.ncd -intstyle xflow -timing toplevel_gen.ngd

toplevel_gen.pcf

#----------------------------------------------#

Using target part "3s2000fg456-4".

Mapping design into LUTs...

Running directed packing...

Running delay-based LUT packing...

ERROR:Pack:2310 - Too many comps of type "RAMB16" found to fit this device.

ERROR:Map:115 - The design is too large to fit the device.  Please check the Design Summary section to see which resource requirement for your design exceeds the resources available in the device. Note that the number of slices reported may not be reflected accurately as their packing might not have been completed.

NOTE:  An NCD file will still be generated to allow you to examine the mapped design.  This file is intended for evaluation use only, and will not process successfully through PAR.

Mapping completed.

See MAP report file "toplevel_gen_map.mrp" for details.

Problem encountered during the packing phase.

Design Summary

--------------

Number of errors   :   2

Number of warnings : 125

ERROR:Xflow - Program map returned error code 2. Aborting flow execution...

Bitstream Not Created

Timing Analysis Passed

What does this mean? How can I fix this error?

Thank you,

Bogdan

[WillD]

First I would check to see how the FIFO is configured.

Is it configured as a DMA FIFO?

[bogdan_ETH]

Yes, it is configured as a "Target to Host - DMA".

[WillD]

Interesting...

What version of LabVIEW?

Is it correct to assume that is the only code you are trying to compile?

[bogdan_ETH]

Sorry, I forgot to mention that...LAbVIEW 2009. And yes, this is the only loop on the FPGA.vi. I just made up this code to understand how exactly I would save some data on the host for subsequent processing, but I didn't get to that point because the VI on the FPGA does not compile successfully. Do you know of any example of the most basic code for DMA FIFOs between the FPGA and Host Computer? This should be pretty straight forward, but for some reason it's not.

Thanks,

Bogdan

[WillD]

Unfortunately I cannot reproduce the issue based on your image.

I am using LV2010, although I doubt that really matters.

The DMA FIFO should only utilize 1 blockRAM.

I hope someone else can chime in.

[Christian Mergl · Accepted solution]

Hey,

Did you allready try to reduce the FIFOs size?

Christian

[bogdan_ETH]

Thank you Christian. Yes, that worked. I created a FIFO with 10000 elements and apparently that takes up a lot of space (RAM blocks). I reduced it to 1000 elements and it works now.

Thanks,

Bogdan