For the Real-Time target it seems to be common to insert an error in and error out command outside the While Loop in the majority of VIs. Every FPGA code I have seen does not include error in and error out. Is this not good practice to include error in and error out in programs running on the FPGA target?
Very few FPGA functions can cause an error, and the additional logic required to check the error condition consumes resources and can slow execution, so error wires are rarely used in LabVIEW for FPGA.
