[fpga] Faster communication between FPGA and real-time host

[WarWolf]

Thank you dan_u! I tried without the IP address and was able to transfer single point data as fast as 4 us.

[dan_u]

Glad that helped. Did you use DMA or FPGA read/write in the end?

I guess avoiding the TCP stack will help in both cases, but I only know for sure for DMA. So for single points as in your use case the read/write control might be more efficient.

[LBJ_GOAT]

Hello,

Do u mind sharing a screenshot from where exactly did u remove the IP address? 

[dan_u]

If you just look at the screenshots in this thread you see the IP address in the resource string.

So instead of "rio://131.151.25.225/RIO0" you just use "RIO0".

[LBJ_GOAT]

I am using the Open FPGA VI reference function and in it I am selecting directly the VI on the FPGA to which I want to connect. Hence I am not providing the address with the IP address. Any idea on how to resolve the same issue in my case?

[LBJ_GOAT]

I have attached a screenshot of what I am doing.

 

[dan_u]

After closing that dialog the "Open FPGA VI Reference" node will have a resource name input (just like in the screenshots posted earlier in this thread). This is where you need to specify where to run the code.

[LBJ_GOAT]

This is what I am seeing after I close the Open FPGA VI reference box.

Here is what I am trying to do,

I am trying to achieve the position control of a DC motor according to the cascaded control.png. I have established the innermost current controller on the FPGA and it is running at a loop rate of 8 kHz. I am just passing the a sinusoidal setpoint to the current controller as reference and reading the some indicators from the VI running on the FPGA. I am using a RT target NI SbRIO 9627 and using the FPGA card sitting on this target. The maximum loop rate that I am able to get is 588 Hz for the RT vi. I suspect the read/write control to the FPGA is taking up significant time to execute, thus limiting the loop rate. Can someone help me, on how I can run my code faster?

[James_McN]

What rate are you trying to achieve? In the best case on these processors, 10kHz is hard, 1kHz is more realistic as a rule of thumb. Faster than that and you may need an outer loop on the FPGA as well.

There are a couple of things in your RT code you could improve on:

• Do the tuning parameters need to be written in every loop? Each input/output to the FPGA takes time (on the order of 10s us from memory) so setting these values once before entering the loop will help. Or updating them from a seperate loop that runs slower should be possible. I can't recall if this may impact the performance of this loop but certainly less than
• Move as many front panel items out of the loop as possible. These all require additional overhead so removing them from the loop will help. If you can move the tuning parameters out anyway then that is a big cut anyway. Other items like the charting are trickier so I would start with the parameters first. There is some guidance on techniques in https://www.ni.com/docs/en-US/bundle/labview-real-time-module/page/lvrtconcepts/passing_data_between... - my first preference in this case would probably be to global variables for the parameters and then perhaps an RT FIFO for the charting to another loop.

These are really not the same as the original issue so you may be best to create a new forum thread with a more relevant title to attract more attention.

[LBJ_GOAT]

Thanks for your quick reply James_McN. I am trying to achieve a loop rate of 2.5 kHz on the the real-time vi. While the inner current control loop on the FPGA is running at a loop rate of 8 kHz. In regards to the suggestions that you provided,

• Can you show through a simple block diagram how I can set the tuning parameters only once? Say if I set the tuning parameters only on the first iteration of the while loop, then how will these values be communicated from the real-time host vi to the FPGA vi during the subsequent iterations? Also, this might lead to some damage of the mechanical system that I am currently testing.
• Can you show how to remove the front panel items out of the loop as you have suggested through some simple block diagram? 
• I have used a timed loop and instead of merged signal function i have used a cluster block for the charting. This has led me to achieve the loop rate of 2.5 kHz consistently. I am using a timed loop to do the same. I have attached my code below. Can you go through my code once, and if possible can you suggest how I can optimize it further?
• When I replace the timed loop with a while loop, and benchmark my code, I can observe a lot of jitter being present in the code. I have used the benchmarking project available in one of the LABVIEW examples to provide a timing analysis of my code. The amount of jitter present in some iterations is extremely high. Can you please shed light on why this is the case?