@maherhome wrote:
We have other FPGA projects with subvi's where compiling the root FPGA vi apparently compiles all subvi's. However, in a new project I seem to have to compile the subvi, THEN compile the parent/root VI. If I only complie the parent, changes in the subvi don't seem to get incorporated.
Does this make sense?
No it makes no sense apart from the fact that I've seen similar problems on RT systems.
When using inlined VIs (And VIs on FPGA are generally inlined) then many changes in sub-VIs don't propagate up to the parent. What I do is make a small change in the parent (relinking a global or something trivial and then compile, that way LV HAS to recompile the parent VI and it automatically retieves the current state of all the sub-VIs.
I've never run into this problem on FPGA (AFAIK). But it certainly sounds familiar.
Shane
