Hello,
this post concerns about "how to clone" xilinx coregen blocks from VI to another VI.
Let me explain the problem:
I have created a FPGA VI in which there are many XILINX blocks generated via CoreGen tool ( for example a Xilinx adder block ). This VI has been debugged and works fine.
- Now, I create a subVI internally to this VI and I want to include one of these Xilinx adders (with the very same parameters, of course). As soon as the subVI is created the arrow of the simulation appears broken. The problem is that the Xilinx block has lost its dependence files and requires the re-generation of the block.
- As stated above, the same thing happens when I want to copy some Xilinx blocks from a VI to another VI, in practice all copied blocks require to be re-generated. This wouldn't be a problem for just one block, but when the blocks are many? Why re-generate many blocks, since each Xilinx block has already the relevant sub-files?
A trivial case: I make a test VI to check the functionality of a CoreGen generated Xilinx block. I generate it, it works. Then, I want to add the block to my "real" project VI. In principle, I should generate it again.. this is a real waste of time, since all the generated (sub) files are already present.
is there someone that have solved this problem ?
I hope the issue is posted in a clear way... Thanks
