25 ns is your clock period at 40 MHz, so the jitter is unavoidable at that clock rate. The square wave DDS algorithm produces a very accurate frequency over time, but can't control the rate at which it's called for updates.
If you set the loop clock to a higher derived clock frequency, you'll cut down the jitter by the same factor. Right-click on the 40 MHz Onboard Clock in the project under the FPGA target and choose New FPGA Derived Clock. You might have to experiment a bit to see how high you can set the clock rate without introducing timing violations in the compile; newer targets will allow higher clock rates in general. Set your single-cycle timed loop to use the derived clock, and also don't forget to update your Square Wave configuration with the new clock rate.
