fpga bit file to debug mode

[jyang72211]

I have some questions on about my FPGA VI.  The host VI is configured to run the bit file version of the FPGA VI, and it runs on the FPGA target.  I just changed the code, and I want to step through it, so I did the following:

1. In my lvproj, I configured the fpga target to execute VI on develoment machine with real I/O.  This is necessary step, right?

2. In my host VI, I have a open fpga reference node.  It points to a bit file, and I changed it, so that it is pointing to the actual VI.  When I run the host VI, I got error -61159 (see below).  Why is that?

3. I noticed that none of the FPGA reference in subvi are type def.  Should I change them all to type def?  What are the pros and cons?

Error -61159 occurred at Open FPGA VI Reference in [TSV2 Test System] - Main.vi

Possible reason(s):

LabVIEW FPGA: This function is not supported when the FPGA target is configured to execute on the development computer with real I/O.

[nathand]

Not all FPGA devices support the "development machine with real I/O" option.  What FPGA device are you using?  Have you tried the simulated I/O option?  Are you sure that you changed it to refer to a VI and not a bitfile?  I wouldn't be surprised to see that error if you're opening a bitfile.  You mentioned that you're not using type definitions for the FPGA reference, so I would expect you'd see a bunch of broken wires when you change the Open FPGA VI Reference, but you didn't mention that happening.

If you're passing the FPGA VI reference into subVIs, I highly recommend making them type definitions.  If you do not do so, and you make changes to the Open FPGA VI Reference, you'll get a bunch of broken wires going into the subVIs because the configuration of the references will no longer match.  I know I've mentioned this in multiple threads before - maybe even in replies to you - but when you use a type definition for the reference, it doesn't update the way I (and maybe others) expect.  You create the type definition once and never touch it again.  When you update the Open FPGA VI Reference configuration, the type definition automatically updates.  If you try to update the type definition manually instead, those changes may get overwritten.

There's a new option in more recent versions of LabVIEW that's might improve the situation with regard to type definitions, but I'm still using 2009 for my FPGA work.

[jyang72211]

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@nathand wrote:

Not all FPGA devices support the "development machine with real I/O" option.  What FPGA device are you using? 

I am using the PCI-7833R as my FPGA device.  Does it support "development machine with real I/O" option?  How do I find out?  

Have you tried the simulated I/O option? 

I haven't tried the simulted I/O option, because I want the real I/O.  I guess I can also try that.  

Are you sure that you changed it to refer to a VI and not a bitfile? 

Yes, I am sure.

I wouldn't be surprised to see that error if you're opening a bitfile.  You mentioned that you're not using type definitions for the FPGA reference, so I would expect you'd see a bunch of broken wires when you change the Open FPGA VI Reference, but you didn't mention that happening.

Yes, I didn't see any broken wire.

If you're passing the FPGA VI reference into subVIs, I highly recommend making them type definitions.  If you do not do so, and you make changes to the Open FPGA VI Reference, you'll get a bunch of broken wires going into the subVIs because the configuration of the references will no longer match.  I know I've mentioned this in multiple threads before - maybe even in replies to you - but when you use a type definition for the reference, it doesn't update the way I (and maybe others) expect.  You create the type definition once and never touch it again.  When you update the Open FPGA VI Reference configuration, the type definition automatically updates.  If you try to update the type definition manually instead, those changes may get overwritten.

There's a new option in more recent versions of LabVIEW that's might improve the situation with regard to type definitions, but I'm still using 2009 for my FPGA work.

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[jyang72211]

One more question.  I created a boolean control in my FPGA vi, but I can't access the new control in my host vi.  Is it because I am still looking at the bit file, and it has not been recomplied?  What is the best practice?  If you don't see the control in the host vi, how do I finish the program? 

[jyang72211]

Is it true that I can't run FPGA VI on my development computer if I run it by calling it through my host vi?  Is it true that I can only runing the FPGA VI by itself without the host vi?  

[jyang72211]

If I want to convert the FPGA reference into a type def, do I have to go into every subvi with the reference and convert them?

[nathand]

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@jyang72211 wrote:

One more question.  I created a boolean control in my FPGA vi, but I can't access the new control in my host vi.  Is it because I am still looking at the bit file, and it has not been recomplied?  What is the best practice?  If you don't see the control in the host vi, how do I finish the program? 

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If you're opening a bitfile, you will see only the controls that are compiled into that bitfile.  If you open a reference to a VI, then you will see all the controls in that VI regardless of whether it has been compiled.  The best practice - at least in my opinion - is to open a reference to an FPGA VI whenever possible, and only use bitfiles when the VI is not an option (FPGA toolkit not installed, reusing FPGA VIs in multiple projects - although that might be fixed now, some other cases). 

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@jyang72211 wrote:

Is it true that I can't run FPGA VI on my development computer if I run it by calling it through my host vi?  Is it true that I can only runing the FPGA VI by itself without the host vi?  

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No, but it's not immediately obvious how.  Try running your host VI, and after it has already opened the FPGA VI Reference, run the FPGA VI.  The FPGA VI will "connect" to the instance that the host opened.  This works for me.

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@jyang72211 wrote:

If I want to convert the FPGA reference into a type def, do I have to go into every subvi with the reference and convert them?

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Well, not so much "convert" as replace them with the type definition (right-click, replace, select a VI... etc).  But yes, you'll need to do this in each subVI individually.

[jyang72211]

I have some more questions.

1. all of the sudden, if I try to open the main vi and run it by itself, my main vi will have broken wire at the open fpga reference.  The error tells me that  I have to open and run my main vi from its project.  If I do that, it works.  What happened?

2. After I added a boolean in my fpga vi, it will not show up in my host vi.  I had to go into the fpga reference type def and update it from the vi or bitfile for the new variable to show up.  Is that a normal behavior?  

[nathand]

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@jyang72211 wrote:

I have some more questions.

1. all of the sudden, if I try to open the main vi and run it by itself, my main vi will have broken wire at the open fpga reference.  The error tells me that  I have to open and run my main vi from its project.  If I do that, it works.  What happened?

2. After I added a boolean in my fpga vi, it will not show up in my host vi.  I had to go into the fpga reference type def and update it from the vi or bitfile for the new variable to show up.  Is that a normal behavior?  

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1. Why wouldn't you open it within the context of the project?  I would guess this is related to using a VI instead of a bitfile, since an FPGA VI may be dependent on items defined in the project such as memory blocks and FIFOs.

2. I don't think that's normal, but as I mentioned previously, if you bind the type definition to the Open FPGA VI Reference, you should never manually update the type definition.  Did you bind the type definition?  If not, that might be the problem.

[jyang72211]

what did you mean by binding type def?  I just converted all of them to type def.  Is that binding?  What did you mean by binding?