fpga compile time

[fmnieuwenhuizen]

I have an FPGA program that requires 4 hours to compile. For doing any serious fast-pace developement and testing this is too long, so I was wondering what can be done to assure the fastest possible compile time. I have a 3GHz processor and 3GB of RAM to reduce the amount of swapping taking place.
Are there any other steps that I can take to cut the compile time down (e.g. is there a way of using multiple computer for compiling)?

Thanks for you reply,

Frank Nieuwenhuizen

[Plamen]

Hello,

it is not possible to use multiple computers for compiling the VI.
You can upgrade your PC - or take a Server with a Processor with one core (multicore processors slow down the process).
This is the only way to make the compilation faster.

Plamen

[fmnieuwenhuizen]

Thanks for you reply. As I am actuallly using a PC with 2 cores, I will be looking in to getting another with only 1.

Regards, Frank

[Plamen]

Hallo again,

I will explain it more in detail.

The compiler uses only one core for compilation. So it will not run faster or slower if you have use a multicore processor instead of a single-core processor.
To increase your performance you can expand your RAM.
In this case the compiler will probably not use a swapfile on the harddisk.

How often do you have to compile your application?
And what platform do you use? (PXI with expansion chassis or cRIO)

Plamen

[fmnieuwenhuizen]

Hi Plamen,

I noticed that only one core is being used, thanks for the clarification.
Your suggestion about increasing the RAM is what I did first before posting to this forum. I went from 1GB to 3GB to make sure that the swap file would not have to be used. However, this did not affect the compile time (at least not significantly).
I am using a cRIO9012 with FPGA 9101 with LV8.2.1 and associated FPGA/NI-RIO/Real-time software. The reason why I have to compile my program so often is because I am developing an SPI interface for an Inertial Measurement Unit (IMU) and need to debug this while communicating with a main host-vi (which can not be done with the emulator, than I could only run the fpga-vi by itself) to get the timing of reading and writing of bits correct.

Thanks for any further comments/insights you have.

Frank

[ThSa]

Frank,
the problem you are running into is that the 1M FPGA seems to be frankly at the limit.
As the case my be we have certain options to get rid of this issue.

a) For testing scenarios try to compile only those parts of the FPGA code which are necessarily required. If this is not possible the options (b) and/or (c) can be a workaround.
b) You know that the code fits on a 1M FPGA. For the tests you might take also a 3M FPGA
c) You did not try to change the compiler optimization method. Since FPGA 8.0 the default setting of the optimization method is "speed". Sometimes the skip to "area" delivers a more satisfying result.
    -> How Do I Change the FPGA Compiler to Optimize for Area or Speed?

Pls let me know if you need any further assistance,
ThSa

[fmnieuwenhuizen]

Hi ThSa,

option a) also came to our mind, I will certainly implement this. Also c) seems like something to try and check out. However, option b) is not feasible for us, acquiring a new device is to expensive. I will have to do with the hardware we already have, but I hope to get everything working as efficiently as possible with options a) and c).

Thanks, Frank

[fmnieuwenhuizen]

As a follow-up on the issues in this thread and a tip for people with similar problems:

after some careful analysis of my program and compilation of parts of it I found out that a large array was causing the long compile time. I had an 1D-array with length 536 somewhere in my program, and when I replaced it with something smaller, the compile time went down from 8 hours to 20 minutes.
I still use 1D-arrays with length 160 in my program, so I do not know where exactly the boundary is where the compilation time explodes. At least be warned when using very large arrays!

Frank