fpga dma fifo size

[elh]

Hello,

I have a question. I'm using a FPGA card (7852R) for measuring an analog input. I trigger the measurement with the digital input which I also measure because my analog signal is multiplexed by the digital signal.  So when the bit sample has changed, which occurs every 2 us the analog signal is being captured. I did a DMA FIFO to send the analog and digital values at once, because on the host I demultiplex my anolg signal taking my dio signal. My fpga fiffo has a depth of 1023 and when I read the samples out of the Host fifo I see that I loose data. I read continously 200 number of elements with my Invoke method and with this number I can see the data streaming on my display. I thought I loose data because I should get´more number of elements at once so I tried some other constalation, but then I dont see any data streaming on my display. It is like the programm ist not doing anything. Has someone any idea which parameters for DMA FIFI  are the best??

Thanks, elh

[Hillman]

Hi Elh,

Thanks for the post.

Its a good start that your using FIFOs.

Could I firstly refer you to this link, where I suggest some useful links.

If you can't stop the issue with the FIFO setup - then place detail how you set them up and I will try to help.

Kind Regards,  

[elh]

Hi Hillmann,

thank you for your reply and for the hints about the RT Fifo. On the fpga vi I can not use a RT Fifo. I use a DMA FIFO  ( target to host) with a depth of 1023. On the host.vi I have an invoke method for reading out  of the dma fifo. There I read 200 elements at once which are beeing processed in a for loop. See my  screenshot above  or just take a look at my project attached now. There you also can see how I created my tartget to host dma Fifo . Is there a method where I can see if fifo has overflow or is empty  for example?? You can do this on the FPGA Target but not on the host! I think my processing after reading the data takes quite a long time so some of the data in the fifo might be overwritten. Or do you have another idea why I loose data? 

Thank you for your help!

elh 

[Ken_Tobler]

What do you mean with you loose data?

You read 200 values and the next 200 aren't the direct following or already inside the 200 package there is some loss of data?

You can read on the Host the status of the FIFO by using the same invoke node, reading 0 values and setting a timeout of 0.

On the "Elements Remaining" output you can see how many elements are in the FIFO.

If it is always on 1023 then you have a FIFO which is too small or you aren't reading out fast enough. In this case the FPGA cannot write in the full FIFO (Timeout -1)

At best set a different Timeout value and check the "Timeout?" output.

Regards

Ken

[Hillman]

Hi Elh,

Sorry for the delay - Im glad to see ken has given you some advice.

I think Ken has given some good advice.

So, you think your losing data because it takes you a long time to do post-processing and thus before you can read the next 200 values (think you should read the whole FIFO, otherwise you'll overflow at some point) you think the FIFO is being overwrite - it could well be.

Some advice on structure of your of the code: I would use the producer/consumer loops - where you read the data out of the FIFO in one loop, enqueue the data and send it to a second loop which can post-process the data, this loop can run slower than the acquire loop and no data will be lost. 

Please let us know how your getting on, 

[AELmx]

This is really old, but the last post is very interesting.

For the producer/consumer loops, for example if it is an array the data being send to the DMA, pass it between loops with a local variable?

This point is interesting, I'm not sure if sending data to DMA can delay the data acquisition.