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fpga

Hello everybody,

 

I am doing a labview fpga programme. I just wnated to generate some variable  delay. I can use delay element in High throughput math and also structures function which can be a fixed delay but i need variable delay. Hence i used memorys to that one. For address i generated a counter and while writing direct adress giving and while reading address-delay given so as to if its writing at 100 smaple then reading starts 0 if my delay 100 samples. Now the problem is while loop is repeating then again and again i am getting delay but i dont want it. Starting itself delay shud come for next loops delay shud nt come. I wrote simple logic (u can see in image)  to that i succeded. The logic is when counter <Delay then reading address must be max memory elemets-delay which is 0 because no element written at that time. But after running memorys written and but not cleared untill we write again so if i run next time the previous data is coming which shud not i want. So how to clear memorys after completetion of iteration?? How can i modify the code to generate delay after running for first iteration only... kindly go through the logic i wrote in image...

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If you want a delay, then do NOT use the Single Cycle Timed Loop.  Just use a normal While Loop.  Then use the Wait function.



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Do you meant to say that creating some sample delay is impossible??? I must use SCTL only..

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@maheshkumar0459 wrote:

Do you meant to say that creating some sample delay is impossible??? I must use SCTL only..


Why must you use the SCTL?  There is nothing in the spec of an FPGA that says that.  And the point of the SCTL is to tell everything in the loop to run in a single clock cycle.  If you need a delay, then not everything can run in a single cycle.  You are just making things more difficult.



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Hav glance on my code wt logic i used. with that im able to generate delay of respective smaples but when i run again the last memorised samples coming again....

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