fpga

[MuratG]

Hi Efosa,

I am still working on cRIO and nothing has finished...

First of all, as I said before cRIO compilation fails when I use a comparision element and the rest that I tried (logic, math, array) is OK.

I think there is a mapping error when a comparision (IF GREATER, IF LESS, IF EQUALS TO 0 etc) mapping of the IF statement

elements fails. This seems a bit strange but in my opinion the xilinx FPGA chip or the compile server has a bug related with the IF

statements and this bug is the first one in ni.com. In the previous message, I have written the web page on the xilinx web site about the 661

error. The bug should be the same with this error.

I wonder if the chasis ni-9104 has been damaged or there is a physical error in its circuitry?

When I do not use a comparision element the cRIO works fine (I send a working FPGA vi). Also I tried the diff analog input module

ni-9215 and it works fine without comparision...

By the way, my problem with cRIO is not its technology or its incapability. As I mentioned before we do not have a lot of time and for our

project still I could not write a code to measure the RMS or Reactive power of the input signals.

Thak you for your attention Efosa. I am looking forward your reply.

[MuratG]

The attachment could not be sent and I am re-sending it.

[MuratG]

The attachment could not be sent and I am re-sending it.

[Efosa O.]

engt, Hope you had a good weekend.

I was able to speak with one of the guys in our R&D team and he informed me that they are currently investigating the error and will notify me once they find anything.

In any case, I want you to know that it is not a hardware issue at all. This is because when you compile FPGA code, you do not necessarily need to have the hardware connected.

It is more than likely a problem with the Xilinx compiler trying to communicate with LabVIEW FPGA. A workaround will be to install the compile server and Xilinx into a different computer and target the FPGA to use the remote compile server. Here are details on how to do that. Please post and let us know how it goes.

Cheers,
Efosa O.

[MuratG]

Hı Efosa,

I think these things are wasting my time. Again I am writing my problem:

The cRIO FPGA works fine if there is no COMPARISION element (greater? etc) All the elements under the COMPARISION group cannot be used.

ALL THE OTHER CODES WORKS. Reading analog input from 9201 and setting the output of digital I/O 9474 and other VI's works.

If you are right then How would the other VI can work????????

PLEASE PLEASE PLEASE

Give me a reasonable solution. AGAIN I am writing the problem:

The cRIO FPGA works fine if there is no COMPARISION element (greater? etc) All the elements under the COMPARISION group cannot be used.

ALL THE OTHER CODES WORKS. Reading analog input from 9201 and setting the output of digital I/O 9474 and other VI's works.

And PLEASE go to google.com and search MapLib Error:661 and read the web page on web site.

Or I am pasting the web site here .............. (I think nobody have ability to use google.com)

Answers Database

LogiCORE Adder/Subtractor v6.0 - NGDBuild issues warning: "WARNING:NgdBuild:452 - logical net 'Q_C_OUT' has no driver" and MAP issues error: "ERROR:MapLib:661"

Answer Record:	20089
Family:	Software
Product Line:	LogiCORE
Part:	Coregen Add/Sub
Version:
Last Modified:	03/09/05 09:37:04
Status:	Active

Problem Description:

Keywords: COREGenerator, MAP, translate, C_OUT, carry, overflow

Urgency: Standard

General Description:
When I use the Adder/Subtracter Core v6.0 provided with COREGen, the following warning occurs in NGDBuild and the following error occurs in MAP:

"WARNING:NgdBuild:452 - logical net 'sum_of1p' has no driver"

"ERROR:MapLib:661 - LUT3_L symbol "clip8_01_U1__n0000<0>1" (output
signal=clip8_01_U1__n0000<0>1/O) has input signal "sum_of1p" which will be
trimmed. See the trim report for details about why the input signal will
become undriven."

Solution 1:

These error and warning messages might be caused by the Adder/Subtracter Core v6.0. An incorrect setting for the carry and overflow options regarding the output size/type will cause these messages.

Refer to the Core Data Sheet table "Availability of Carry/Borrow/Overflow Outputs and Output Data Type/Size Against Input Data Type" at:
http://www.xilinx.com/ipcenter/catalog/logicore/docs/addsub.pdf

This is not an issue in Core version 7.0 since COREGen does not allow the conflicting setting.

However, if the Core is upgraded from version 6.0 to 7.0, you must regenerate the v7.0 Core from scratch.The COREGen GUI feature "File -> Execute Command File" allows you to select the XCO file generated from v6.0, but do not use the v6.0 XCO file. Instead, generate the v7.0 Core from scratch.

[MuratG]

OK?

AGAIN Our cRIO works fine unless there is no element under Comparision group. The rest is OK?

and Efosa, PLEASE give me a reasonable solution, I am tired to writing here and sending my problem to ni.com/support and after 3 weeks I have only a cRIO does not work properly and nothing and nothing.... I have only void solutions from NI and nothing and nothing

and Efosa PLEASE PLEASE read the xilinx.com web page and give me the solution about it. xilinx FPGA users have the same problem ERROR 661 and AGAIN PLEASE

stop giving void solutions. May be the NI guys cannot understand but the problem is comparision elements OK?

I am tired and has NOTHING except non-working cRIO THE GREAT CONTROLLER which cannot compare TWO BASIC SIGNALS

thats all now

[MuratG]

by the way

your las solution DOES NOT work

now

Do I have to re-re-re-re-install LabVIEW and the others again ? Or do I have to re-re-re-re-control the connections? Is your next solution is cut the power off and then

energize the cRIO again? I am saying before your next solution:

DOES NOT WORK

Message Edited by engt on 06-12-2006 10:55 AM

[MuratG]

again hi Efosa,

I disconnected all the I/O modules and the system is only 9004 and 9104 and I compiled the FPGA code (attached) and the compile server message is again the same.

...

#----------------------------------------------#
# Starting program map
# map -o toplevel_gen_map.ncd -intstyle xflow toplevel_gen.ngd toplevel_gen.pcf
#----------------------------------------------#
Using target part "2v3000fg676-4".
Mapping design into LUTs...
ERROR:MapLib:661 - LUT4 symbol "mytop/n_273284056/PlainIndicator/_n00011"
   (output signal=mytop/n_273284056/PlainIndicator/_n0001) has input signal
   "mytop/n_270207072/n_270269512/xgty<0>" which will be trimmed. See the trim
   report for details about why the input signal will become undriven.

Error found in mapping process, exiting...
Errors found during the mapping phase.  Please see map report file for more
details.  Output files will not be written.

Design Summary
--------------
Number of errors   :   1
Number of warnings :  12
ERROR:Xflow - Program map returned error code 2. Aborting flow execution...

by the way did anybody read the xilinx.com and understand what is error 661? or still working on the what is the next SOLUTION ?

[Efosa O.]

engt,

Would you mind if one of the engineers here at NI contacts you. After speaking with R&D, it seems like we will need some more information from you regarding this issue.

We are doing our best to make sure we get you up and running, but having direct communication with you via phone will be better.

Please let us know. Thanks

Efosa O.
NI-AE

[MuratG]

of course it may be more advantegous. my contact information is available at my account informations and here the time is GMT+02:00.