generation and acquisition

[Salvio]

Hi again JMOTA...i'm sorry if i'm so persistent and annoying but next week i will have my thesis and i want to try to make it works

I've tought that a solution can be this but i cannot try it because now i'm at home...:

first of all i have the FPGA INVOKE NODE  than i have another block of the FPGA in which i set to false Generation and Acquisition (as shown in the photo)

http://img72.imageshack.us/my.php?image=immagine2kf9.png

after that i've tought to put into only one while loop the generation and the acquisition (in the VI i've posted in the others replies i've done two while loop one for generation and one for the acquisition and this creates me some problem because to stop the VI  i need to abort the execution and this is not good for me because doing this i lost the control of the cRIO).

So in this "big" while i will have a case structure for the generation and a case structure with the acquisition (as i've done before).

Then i've tought to put out of both the case structure 2 block of the FPGA one for the generation and one for the acquisition (like this one in the photo):

http://img77.imageshack.us/my.php?image=immagineky1.png

that goes to stop the two parallel while loop  (one for the generation and one for the acquisition) in the FPGA and at same time if are both true they go to stop not only my VI (because i put it as condition of the external while loop in which i've put the generation and the acquisition) but at same time go to stop also the FPGA.

What do you think? i'm crazy or will it work?

plz try to analize this my last and desperate solution and give me some advices.

ps: i've put you, christian and all the staff of the NI that have helped me in the thanks of the my thesis

Message Edited by Salvio on 02-18-2007 03:31 AM

[JMota]

Hi Salvio,

Sorry for taking too long too reply. In response to an earlier post, the way you would reset the DMA FIFO, is by reading all elements available in the DMA FIFO from the host, and making sure there are no more elements remaining. Depending on how your FPGA logic is, you may need to wait until you are certain that your FPGA is not writing any more data to the DMA FIFO.

I tried to see the photos you added to your last post, and the second one does not work for me and I'm not sure what exactly you are trying to do. I hope that by this time you have already resolved the problems you were having, or figured out a way to workaround them. Hope your thesis is going (or went) well.

JMota