how do i communicate with host and FPGA?

[roxylat]

hi

 Thank u again for ur answer.Do U mean the following step u mentioned above is similar my project? .So  can i build my idea based on ur tutorial step?

with regards

roxy

[ninlmartijn]

Hello Roxy,

The idea I gave was adjusted especially for your project. It will give you a starting point. Please follow the following steps;

- first make the example (you mentioned) working on your hardware configuration (as described in the tutorial)

- then change te example to your own requirerments. The picture in my precious post will give you a idea hot to implement the three states you mentioned. You can put the three states in a case structure. The example will control the case structure. Depending on the outcome of the example the case structure will go to the right state. Please be aware of the default state, and don't forget to turn the alarm off in the other states below 50.

There are many solutions possible for your problem. The example I made is just one of those which points you to a direction to go.

Best regards,

Martijn

[roxylat]

hi

    Thank u for you are concern.I have already try what u say but still cannot run  with my aceelerometer.Please see my zip file and could u suggest me whether i rite or wrong?

best regards

 roxy

[ninlmartijn]

Hello Roxylat,

Bad to hear that things aren't working until now. Did the example work on your FPGA target, please try to use the example first. I did had a look at your code, and have a few suggestions;

- please verify if the calibration mode of your module is set on 'raw'. You can do that in the module properties (project explorer, right click on your module)

- are you using a smart sensor (TEDS; http://www.ni.com/teds/ ) ? Please use the right setting for this under point 5 of your host vi.

I hope this will help you further, please let me know.

Best regards,

Martijn

[roxylat]

hi Martijin

 yah exmple program work on FPGA target but my modify program dosent work on FPGA target .By the way, every time when i start to run host and FPGA program,i need to download and compile again .Is it correct way ?.

thank ur for ur time

roxy

[ninlmartijn]

Hello Roxy,

Are you using a TEDS sensor? If you enabled TEDS I found a possible fault in the code. In the host VI there is a invoke node above point 5 (case true). At this point there the module slot is specified. Please change this to te correct slot (4 in your case). But this is only when using TEDS. 

Is there data visible above point 9, it's best to create a indicator. We have to verify until what point the data is visible.

Is there a reason for using a sequence above point 10, If it isn't needed, please remove it.

Did you had the chance to look at the module properties? Whese properties can change for each project. Please check if the calibration property is on raw data on the module in the project window (with the file you send this property is callibrated, this is not possible wth this example).

It is possible to save your bit file in the memory from te FPGA target. hen the FPGA target powers up, the memory will be loaded. Please find the helpfile under the following link;  http://zone.ni.com/reference/en-XX/help/371599A-01/lvfpgahelp/downloading_fpga_vi_to_flash/

Have a great weekend!

Best regards,

Martijn